臺灣博碩士論文加值系統

近年來，由於半導體技術的進步，金氧半元件在尺寸上的縮小化，有著顯著的成果。根據國際半導體技術藍圖（ITRS）的預測，西元2012年時，元件上的等效氧化層厚度將會達到0.5奈米，此時的矽氧化層因為太薄而易產生大量漏電流，影響元件上的電特性，進而產生穩定度的問題。由於氧化層的特性在超大型積體電路元件的表現及可靠度上扮演著極為關鍵的角色，因此，在高介電質材料做為元件絕緣層的相關問題尚未解決之前，如何提升二氧化矽介電層的品質仍是目前非常重要的課題。在本篇論文中，我們提出一個用機械應力彎曲矽晶圓的方式，使矽晶格產生應變，並將此伸張應力分別應用在成長二氧化矽氧化層時及金氧半元件製程之後，並且利用傾斜陰極之陽極氧化系統生長不同厚度之氧化層，探討此機械應力對其電特性及穩定性的影響。實驗結果證明，無論是張力成長之氧化層技術或伸張形變溫度施壓技術，都能增進金氧半元件的氧化層品質。另外，我們在最後對此技術提出未來的研究方向。

In recent years, due to the advanced technology of semiconductor, there are great results in the scaling of MOS devices. Based on the International Technology Roadmap for Semiconductors (ITRS), the equivalent oxide thickness (EOT) should be 0.5 nm in 2012 and high gate leakage current will be produced because the thickness of oxides becomes thinner. The leakage current will make the device lose its electrical characteristics and cause reliability problems. The quality of oxide plays a critical role to the device performance and reliability of ultra-large scale integrated circuits. Therefore, it is still an important topic to promote the quality of silicon-dioxide dielectrics before the problems of high-κ gate dielectric be solved. In this thesis, the strained silicon concept by applying mechanical tensile stress on silicon was proposed. The tensile stress is applied on oxidation and after sample preparation, separately. The electrical characteristics and reliability of different thick oxides prepared by tilted cathode anodization system will be discussed. From the experimental results, the quality of MOS gate oxides would be improved by either tensile-stress oxidation or strain-temperature stress. Finally, conclusions and some other suggestions for future work about this thesis were given.

摘要 I
Abstract III
Content V
Figure Captions VII
Chapter 1 Introduction 1
1.1. Motivation of This Work 1
1.2. Measurement Tools and Equivalent Circuit Models of MOS Capacitors 4
1.3. Anodization and Anodized Oxide 8
1.4. Summary 9
Chapter 2 MOS Capacitors with Oxides Grown by Tilted Cathode Tensile-Stress Anodization 13
2.1. Introduction 13
2.2. Experimental Setup 15
2.3. Results and Discussion 16
2.3.1. C-V & I-V Curves 17
2.3.2. Flat-band Voltage Shift 18
2.3.3. TDDB Reliability 21
2.3.4. Oxide Growth Kinetics 23
2.4. Summary 24
Chapter 3 MOS Capacitors with Strain-Temperature Stress 39
3.1. Introduction 39
3.2. Experimental Setup 41
3.3. Results and Discussion 42
3.3.1. C-V & I-V Curves 43
3.3.2. TDDB Reliability 44
3.4. Summary 46
Chapter 4 Conclusions and Future Work 57
4.1. Conclusions 57
4.2. Future Work 58
References 61

[1]W. Shottkley, “Semiconductor translation device,” U.S. Patent 266814, filed 1949.
[2]Jack S.Kilby, “Semiconductor Device-and-Lead Structure, July 30, 1959,” U.S. Patent 2918877, April 25, 1961.
[3]G. E. Moore, “Progress in digital integrated circuit,” IEDM tech. Dig., p.11, 1975.
[4]International Technology Roadmap for Semiconductors (ITRS), 2007 Edition.
[5]E. H. Nicollian and J. R. Brews, “Interface traps:bond models” MOS Physics and Technology, pp.823,1981.
[6]C. H. Choi, Y. Wu, J.S. Goo, Z. Yu, and R. W. Dutton, “Capacitance reconstruction from measured C-V in high leakage, nitride/oxide, MOS,” IEEE Trans. Electron Devices, vol.47, pp.1843-1850,2000.
[7]A. Nara, N. Yasuda, H. Satake, and A. Toriumi, “Applicability Limits of the Two-frequency Capacitance Measurement Technique for the Thickness Extraction of Ultrathin Gate Oxide,” IEEE Trans. On Semicon. Manufacturing, Vol. 15, pp. 209-213, 2002.
[8]K. J. Yang and C. Hu, “MOS capacitance measurements for high-leakage thin dielectrics,” IEEE Trans. Electron Devices, vol. 46, pp. 1500-1501, 1999.
[9]Yang, K.; Ya-Chin King; Chenming Hu; “Quantum effect in oxide thickness determination from capacitance measurement,” VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on 14-16 June 1999 Page: 77-78.
[10]Berkeley Device Group. [Online].
Available http://www-device.eecs.berkeley.edu/index.htm.
[11]Hamada A., Furusawa T., Saito N. and Takeda E., “A new aspect of mechanical stress effects in scaled MOS devices,” Electron Devices, IEEE Transactions on Vol. 38, pp. 895-900, 1991.
[12]Gallon C., Reimbold G., Ghibaudo G., Bianchi. R. A., Gwoziecki R., Orain S., Robilliart E., Raynaud C. and Dansas H., “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” Electron Devices, IEEE Transactions, Vol. 51 pp. 1254-1261, 2004.
[13]C. C. Ting and J. G. Hwu, “Low Leakage and High Breakdown Endurance Ultra-thin Gate Oxides Prepared by Anodization Technique,” Master Thesis, Dept. of Electrical Engineering, N.T.U. 2000.
[14]Rim K., Hoyt J. L. and Gibbons J.F. “Fabrication and analysis of deep submicron strained-Si n-MOSFET’s,” IEEE Transactions on Vol.47, pp. 1406-1415, 2000.
[15] Nayak D. K., Goto K., Yutani A. Murota J. and Shiraki Y., “High-mobility strained-Si PMOSFET’s,” IEEE Transactions on Vol. 43, pp. 1709-1716, 1996.
[16] Sugii N., Hisamoto D. Washio K., Yokoyama N. and Kimure S., “Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical polished SiGe substrate,” Electron Devices, IEEE transactions on Vol.49, pp.2237-2243, 2002.
[17] Maikap S., Yu C. Y., Jan S. R., Lee M. H. and Liu C. W., “Mechanically strained strained-Si NMOSFETs,” Electron Device Letters, IEEE, Vol. 25, pp.40-42, 2004.
[18]T. S. Chen and Y. R. Huang, “Evaluation of MOS devices as mechanical stress sensors,” Components and Packaging Technologies, IEEE transactions on Vol.25, pp. 511-517, 2002.
[19]T. H. Lee and J. G. Hwu, “Investigation of Ultra-thin Gate Oxides Prepared by Anodization with Tensile Stress in Tilted Cathode Anodization System,” Master Thesis, GIEE, N.T.U. 2006.
[20]S. W. Huang and J. G. Hwu, “Electrical Characterization and Process Control of Cost Effective High-k Aluminum Oxide Gate Dielectrics Prepared by Anodization Followed by Furnace Annealing,” IEEE Transactions on Electron Devices, Vol.50, No.7,, PP.1658-1664, Jul. 2003.
[21]C.C.Wang, T.H.Li, K.C.Chuang and J.G.Hwu*, “Ultra-thin Gate Oxides Prepared by Tensile-Stress Oxidation in Tilted Cathode Anodization System,” Journal of the Electrochemical Society, 155 (s), G61-G64, 2008.
[22]N. W. Ashcroft and N. D. Mermin, Solid State Physics, pp. 32-38, Holt,Rinehard, and Winston, New York, 1976.
[23]C. H. Tseng, “Germanium Channel MOSFETs and Strain-Induced Effects on Silicon MOS Capacitor”, p69.
[24]Degraeve, R., et al., “A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides” in IEDM, p.863, 1995.
[25]Harari, E., “Dielectric breakdown in electrical stressed thin films of thermal SiO2” J. Appl. Phys., 1978. 49(4): p.2478.
[26]Rico, B., M. Y. Azbel, and M.H. Brodsky, “Novel Mechanism for Tunneling and Breakdown of Thin SiO2 Films,” Phys. Rev. Lett., 1983. 51(19): 1795.
[27]Nissan-Cohen, Y., J. Shappir, and D. Frohman-Bentchkowsky, “Trap generation and occupation dynamics in SiO2 under charge injection stress,” J. Appl. Phys.,1986. 60(6):2024.
[28]C. C. Wang and J. G. Hwu, “High Quality Ultra-thin Gate Oxides Prepared by Tensile-Stress Anodization Technique,” Master Thesis, GIEE, N.T.U. 2007.
[29]J. Y. Yen and J. G. Hwu, “Enhancement of Silicon Oxidation Rate due to Tensile Mechanical Stress,” Applied Physics Letters, Vol.76, pp.1834-1835, 2000.
[30]Zhu, N., Van Wyk, J. D. and Liang, Z. X., “Thermal-mechanical stress analysis in embedded power modules,” Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE 35th Annual, Volume 6, 20-25, June 2004, pp. 4503-4508, Vol.6.