臺灣博碩士論文加值系統

本論文主要為實現X-band的雙平衡混頻器電路及具有鏡像抑制之C-band升、降頻混頻器電路，利用穩懋半導體公司 ( WIN ) 所提供的模型進行下線，分別採用WIN 0.5 μm &0.15 μm pHEMT製程技術。
在X-band為一個Gilbert cell 雙平衡混頻器電路，利用電感諧振技術在12 GHz 轉換增益約有8 dB，RF可用頻率約從5~20 GHz，P_1dB點約為-16 dB，以及IIP3為6 dBm，消耗功率為 59.8 mW。
在C-band利用相位相消的方式將鏡像訊號抑制，分別為升、降頻混頻器電路，升頻混頻器電路轉換損耗約為30 dB，鏡像抑制比在要求頻段內皆大於20 dB，各端的隔離度皆大於20 dB，IIP3約為-4 dBm，總消耗功率為120 mW。而在降頻混頻器部分轉換增益約為0.5 dB，鏡像抑制比在頻段內皆大於21 dB，IIP3約為-4.5 dBm總消耗功率為63 mW。

In this thesis，X- and C-band mixer circuits with image rejection functions have been realized by using 0.5 μm pHEMT and 0.15 μm pHEMT process, respectively.
The X-band Gilbert cell down-conversion mixer was designed at 12 GHz with the bandwidth from 5 to 20 GHz. An extra inductor was added to enhance the conversion gain. The conversion gain is 8 dB, is -16 dBm，IIP3 is about 6 dBm, and total power consumption is about 60 mW.
For C-band image rejection down- and up-conversion mixers, the image signal can be suppressed by phase cancellation approach. The measured results of up-conversion mixer show that the conversion loss of -5.5 dB and image rejection ratio of 20 dB in desired band, isolation between each port is better than 20 dB, and IIP3 is -4 dBm with power consumption of 120 mW. Moreover, the measured results of down-conversion mixer show that the conversion gain of 0.5dB, image rejection ratio of 21 dBm, and IIP3 of -4.5 dBm with power consumption of 63mW.

指導教授推薦書.....................i
口試委員審定書....................ii
授權書.....................................iii
誌謝......................iv
摘要....................................v
Abstract..............................vi
目錄.............................vii
圖目錄...........................ix
表目錄............................xii

第一章 簡介( Introduction ) 1
§1.1 研究動機 1
§1.2章節概述 2
第二章 基本理論簡介 4
§2.1 簡介 4
§2.2射頻混頻器主要特性的定義 5
§2.2.1 轉換增益 ( Conversion Gain ) 5
§2.2.2 隔離度 ( Isolation ) 6
§2.2.3 1dB增益壓縮點 ( P1dB ) 7
§2.2.4 交互調變 ( Intermodulation；IMD ) 8
§2.2.5 雜訊指數 ( Noise Figure；NF ) 9
§2.3混頻器之工作原理 10
第三章 運用電感諧振之X-band雙平衡混頻器設計 11
§3.1 單平衡混頻器之工作原理 11
§3.2 雙平衡混頻器之工作原理 13
§3.3 Marchand balun理論分析 15
§3.2 Marchand balun製作與電磁模擬 20
§3.4 運用電感諧振技術之X-band雙平衡混頻器設計與實作 24
§3.5 電路模擬與量測結果 28
第四章 應用主動式巴倫雙平衡相位式消除鏡頻混波器 35
§4.1 相位式消除鏡頻訊號工作原理 35
§4.2 相位式鏡頻消除升頻混波器的架構設計與製作 39
§4.3 升頻混頻器量測結果分析與除錯討論 43
§4.4 雙閘極鏡頻消除降頻混頻器設計與製作 53
§4.5 降頻混頻器量測結果與實作討論 56
第五章 結論( Conclusions ) 63
附錄(appendix ) 65
參 考 文 獻 (References) 76

圖目錄
圖2.1 發射機系統示意圖[1] 4
圖2.2 1dB抑制點之示意圖[1] 7
圖2.3 交互調變乘積項之頻譜示意圖[1] 8
圖2.4 IIP3之示意圖[1] 9
圖2.5 雜訊指數示意圖[1] 9
圖2.6混頻器操作與頻譜示意圖[1] 10
圖3.1單平衡MOSFET混頻器 [2] 11
圖3.2 本地振盪脈波波形[2] 12
圖3.3 雙平衡混波器架構圖 14
圖3.1 Balun示意圖[1] 15
圖3.2 Marchand Balun架構圖[1] 16
圖3.3 Marchand Balun S11分析[1] 17
圖3.4 Marchand Balun S21分析[1] 18
圖3.5 Marchand Balun S31分析[1] 18
圖3.6 Marchand Balun S22分析[1] 19
圖3.7 Marchand Balun S33分析[1] 19
圖3.8 Marchand Balun S23分析[1] 19
圖3.9 Marchand Balun S32分析[1] 20
圖3.10 Conventional & Transformer type Marchand balun 21
圖3.11 Phase difference ( S21-S31 )&Insertion Loss 22
圖3.12 Return Loss 22
圖3.13 Transformer Marchand balun 晶片佈局圖 23
圖3.14 運用電感諧振之X-band 雙平衡架構圖 24
圖3.15 切換對的輸入電壓與雜訊示意圖[7] 26
圖3.16 Current bleeding示意圖 26
圖3.17 混頻器寄生電容示意圖 27
圖3.18 Return Loss of RF port 28
圖3.19 Return Loss of LO port 29
圖3.20 Conversion Gain versus LO power 29
圖3.21 Conversion Gain versus RF power 30
圖3.22 Conversion Gain versus frequency 30
圖3.23 Port-to-port isolation 31
圖3.24 IMD3 31
圖3.25 晶片俯視圖 33
圖4.1相位式鏡頻拒斥混頻器架構圖[13] 36
圖4.2 混頻器動作原理[13] 36
圖4.3 雙平衡正交相位鏡像抑制混波器電路架構 39
圖4.4 雙平衡正交相位鏡像抑制架構圖[19] 40
圖4.5 Active balun 示意圖 40
圖4.6 RC-CR phase shifter示意圖[19] 41
圖4.7 Rat-race hybrid 示意圖與實作 42
圖4.8 5.8 GHz Rat-race insertion loss 43
圖4.9 5.8 GHz Rat-race balun phase difference 43
圖4.10 Conversion gain &Image Rejection Ratio vs LO power 44
圖4.11 Measurement of Conversion gain vs IF power 44
圖4.12 Measurement of RF&LO input return loss 45
圖4.13 Measurement of IF input return loss 45
圖4.14 Conversion gain & IRR vs LO frequency 46
圖4.15 IIP3 46
圖4.16 Port-to-port isolation 47
圖4.17(a) 輸出頻譜圖與鏡像抑制比 47
圖4.17(b) 輸出頻譜圖與鏡像抑制比 48
圖4.18 Micrograph of the proposed mixer 48
圖4.19 升頻鏡像抑制混頻器 實作圖 49
圖4.20雙閘極混頻器示意圖 55
圖4.21 雙閘極混頻器I-V特性圖[2] 55
圖4.22 雙閘極鏡像抑制混頻器架構圖 56
圖4.23 降頻鏡像抑制混頻器量測佈局圖 58
圖4.24 20MHz輸出頻譜圖 58
圖4.25 Conversion gain vs RF power 59
圖4.26 Conversion Gain vs LO power 59
圖4.27 Return Loss 60
圖4.28 Port-to-port Isolation 60
圖4.29 IIP3 61
圖4.30 Simulation of IRR& Conversion gain vs RF frequency 61
圖4.31 降頻晶片之微影圖 62
圖4.32 結合外部LC coupler之實作圖 62

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