跳到主要內容

臺灣博碩士論文加值系統

(216.73.216.106) 您好!臺灣時間:2026/04/04 07:51
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:沈柏村
研究生(外文):Po-Tsun Shen
論文名稱:運用熱回流法製作次微米T型閘極的低雜訊變異結構高電子遷移率電晶體之研究
論文名稱(外文):Low Noise Metamorphic HEMT with Thermal Reflowed Submicron T-Gate
指導教授:張翼張翼引用關係張俊彥
指導教授(外文):Edward Y. ChangChun-Yen Chang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:材料科學與工程系
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:65
中文關鍵詞:回流法變異結構高電子遷移率電晶體閘極長度互導係數電流增益截止頻率最大震盪頻率
外文關鍵詞:reflowMHEMTgate lengthtransconductancecut-off frequencymaximum frequency of oscillation
相關次數:
  • 被引用被引用:0
  • 點閱點閱:275
  • 評分評分:
  • 下載下載:30
  • 收藏至我的研究室書目清單書目收藏:0
本論文的研究係利用電子束微影與回流法製備具有次微米T型閘極的變異結構高電子遷移率電晶體(MHEMT),這種電晶體可以使用於提高頻率(>100GHz)。此研究之In0.53Ga0.47As/InAlAs高電子遷移率電晶體利用InxAl1-xAs作為砷化鎵基板與磷化銦HEMT結構的緩衝層;並藉回流法與電子束微影獲得0.15μm的閘極長度。製備完成的電晶體具有200mA/mm的汲極飽和電流在1.2V源極汲極偏壓下互導係數高達有750mS/mm。雜訊方面,160μm的元件在18GHz的狀態下具有小於1dB的雜訊值及高達13.5dB增益值。元件的電流增益截止頻率以及最大震盪頻率分別到達154GHz與350GHz。此研究所研發出之變異結構高電子遷移率電晶體極適於高頻低雜訊的元件應用。

A metamorphic high electron-mobility transistor (MHEMT) fabricated with reflowed submicron T-gate using E-beam lithography for high frequency electronics application is developed in this study. The In0.53Ga0.47As/InAlAs MHEMT uses InxAl1-xAs as the buffer layer between GaAs substrate and the InP lattice-matched HEMT structure. The reflowed T-gate has a gate length of 0.15μm. The fabricated metamorphic HEMT has a saturation drain current of 200mA/mm and a transconductance of 750mS/mm at VDS=1.2V. The noise figure of a 160μm gate-width device is less than 1dB and the associated gain is up to 13.5dB at 18GHz. This device demonstrates a cut-off frequency fT of 154 GHz and a maximum frequency of oscillation fmax up to 350GHz. The metamorphic HEMT developed in this study has the potential for high frequency low noise applications.

Content
Abstract(Chinese)
Abstract(English)
Acknowledgement
Content
Table Captions
Figure Captions
Chapter 1 Introduction 01
1.1 Motivation for this 01
1.2 Dissertation content 02
Chapter 2 Literature Review 04
2.1 Comparisons of MHEMT, PHEMT and InP HEMT 04
2.2 Selective Etch in Gate Recess 06
2.3 Technologies for Gate Shrinkage 07
2.4 Summary 09
Chapter 3 Experiment and procedures 10
3.1 Device structure 10
3.2 Experiments of Reflow Gate 11
3.2.1 Test sample preparation 11
3.2.2 Reflow procedures and measurements 11
3.3 Device fabrication 12
3.3.1 Wafer cleaning 12
3.3.2 Device isolation 12
3.3.4 Ohmic contact formation 13
3.3.4 Selective etching for gate recess & T-gate formation 14
3.3.5 Device passivation & Contact via 15
3.3.6 Airbridge formation 16
3.4 Characteristic & Measurements 16
3.4.1 Ohmic Contact 17
3.4.2 Current-voltage curve & pinch off voltage 18
3.4.3 Breakdown voltage (VB) 18
3.4.4 Transconductance (Gm) 19
3.4.5 S-parameter 19
3.4.6 Noise figure 20
Chapter 4 Results and Discussions 21
4.1 Reflowed T-gate Test 21
4.2 Mesa Isolation & Ohmic Contact 22
4.3 Gate Recess & Gate Metallization 23
4.4 Au Plating Airbridge Formation 23
4.5 DC characteristics of the MHEMT 23
4.5.1 I-V characteristic for MHEMT 23
4.5.2 Breakdown Voltage (VB) 24
4.5.3 Transconductance (Gm) 24
4.6 RF characteristics of the MHEMT 25
4.6.1 Unit Current Gain Cutoff Frequency (fT) & Maximum Frequency of Oscillation (fmax) 25
4.6.2 Noise figure (NF) 26
4.7 Discussion 27
Chapter 5 Conclusions 28
Reference 30
Table
Figure

※Reference※
1. S.M. Sze, “High-speed semiconductor devices” , John Wiley , 1990.
2. M. I. Alsun et al., IEDM Tech. Digest, p. 822, 1986.
3. M. Tong et al., “Selective wet etching for InGaAs/InAlAs/InP Heterostructure Field-Effect Transistors.”
4. Herve Fourre et al., “Selective wet etching of lattice-matched InGaAs/InAlAs on InP and metamorphic InGaAs/InAlAs on GaAs using succinic acid/hydrogen peroxide solution,” J. Vac. Sci. Technol. B 14(5), Sep/Oct 1996.
5. S. J. Pearton et al., “Selective dry etching of InGaAs and InP over InAlAs in CH4/H2/SF6,” Appl. Phys. Lett. 56(22), 28 May 1990.
6. Hung-Chung Kao et al., “Selective gate recess RIE etching by CHF3+BCl3 in InAlAs/InGaAs HEMTs,” IEEE 1997.
7. “Atomic force microscopy investigations of dry etched gate recesses for InGaAs/InAlAs/InP-based high-electron-mobility transistors using methane-hydrogen reactive ion etching,” J. Vac. Sci. Technol. B, vol. 13 pp 2386-2389, 1995.
8. T. Suemitsu, T. Enoki, H. Tokoyama and Y.Ishii: Jpn. J. Appl. Phys. 37 (1998) 1365.
9. A. S. Wakita et al., “Novel high-yield trilayer resist process for 0.1 um T-gate fabrication.” J. Vac. Sci. Technol. B 12(6), Nov/Dec 1995 2725.
10. M. Nawaz et al., “A novel gate process for InP based HEMTs with gate length from 0.06~0.2μm” IEEE 1999.
11. T. Suemitsu et al., “Improved Recessed-Gate Sturcture for Sub-0.1μm-Gate InP-Based High Electron Mobility Transistors” Jpn. J. Appl. Phys. Vol. 37(1998) pp. 1365-1372.
12. T. Suemitsu et al., “30nm-Gate InAlAs/InGaAs HEMTs Lattice- Matched to InP Substrates” IEEE 1998.
13. Y. Yamashita et al., “High fT 50-nm-Gate InAlAs/InGaAs High Electron Mobility Transistors Lattice-Matched to InP Substrates.” Jpn. J. Appl. Phys. Vol 39(2000) L838-L840.
14. J. R. Chung, S. J. Choi, Y. Kan, S. G. Woo and J. T. Moon: Proc. SPIE3999(2000)305.
15. H. L. Chen, F. H. Ko, L. S. Li, C. K. Hsu, B. C. Chen and T. C. Chu: Jpn. J. Appl. Phys. 41(2002) 4163.
16. H. M. Lee, Edward Yi Chang, S. H. Chen and C. Y. Chang, Jpn. J. Appl. Phys. Vol. 41(2002) pp. L1508-L1510.
17. Ralph Williams, “Modern GaAs Processing Methods,” Artech House Boston London.
18. 本城和彥, “微波通訊半導體電路,” 全華科技圖書.
19.Frank Schwierz and Juin J. Liou, “Modern Microwave Transistors Theory, Design, and Performance,” WILEY INTERSCIENCE (2003).

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top