1. 黃舒意,”台灣年輕族群對消費性電子產品的未來需求”,國立政治大學,國際經營管理英語碩士學位學程(IMBA),碩士論文,2009年。2. 張玉奭,”電子產品之吸引力與進步性效能分析-以筆記型電腦為例,東吳大學,EMBA高階經營碩士在職專班,碩士論文,2008年。3. 鍾文仁、陳佑任,「IC封裝製程與CAE應用」,全華科技圖書有限公司,2006年。
4. Uwww.DfRSolutions.comU。
5. Chang-Ming Liu, Kuo-Ning Chiang,” Solder Bumps Layout Design And Reliability Enhancement of Wafer Level Packaging,” International Conference on Electronic Packaging Technology, pp. 56-64, 2003.
6. Chang-Chun Lee, Shu-Ming Chang, Kuo-Ning Chiang, ”Design of Double Layer WLCSP Using DOE with Factorial Analysis Technology,” Electronics Packaging Technology Conference, pp. 776-781, 2004.
7. Chang-Ann Yuan, Cheng Nan Han, Ming-Chih Yew, Chan-Yen Chou, and Kou-Ning Chiang, ”Design, Analysis, and Development of Novel Three-Dimensional Stacking WLCSP,” IEEE Transactions ON Advanced Packaging, Vol. 28, No. 3, pp. 387-396, August 2005.
8. Chang-Ming Liu, Kuo-Ning Chiang, ”Reliability Enhancement of Wafer Level Packaging Using Solder Ball Layout Methodology,” International Conference on Electronic Packaging Technology, 2005.
9. Ji-Cheng Lin, Hsien-Chie Cheng, and Kuo-Ning Chiang, ”Design and Analysis of Wafer-Level CSP With a Double-Pad Structure,” IEEE Transactions on Components and Packaging Technologies, Vol. 28, No 1, pp. 117-126, March 2005.
10. John H. Lau, S-W. Ricky Lee, ”Reliability of Wafer Level Chip Scale Package (WLCSP) with 96.5Sn-3.5Ag Lead-Free Solder Joints on Build-up Microvia Printed Circuit Board,” Int’l Symp on Electronic Materials &; Packaging, pp. 55-63, 2000.
11. John H. Lau, S-W. Ricky Lee and Chris Chang, ”Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis,” ASME Journal of Electronic Packaging, Vol. 122, pp. 311-316, December, 2000.
12. John H. Lau, Stephen H. Pan and Chris Chang, ”Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-free Solder Joints and Microvia Build-up Printed Circuit Board,” ASME Journal of Electronic Packaging, Vol. 124, pp. 69-76, June, 2002.
13. John H. Lau, Stephen H. Pan and Chris Chang, ”A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints,” ASME Journal of Electronic Packaging, Vol. 124, pp. 212-220, September, 2002.
14. Satish C. Chaparala, Brian D. Roggeman, James M. Pitarresi, Bahgat G. Sammakia, John Jackson, Garry Griffin, and Tom McHugh,” Effect of Geometry and Temperature Cycle on the Reliability of WLCSP Solder Joints,” IEEE Transactions on Components and Packaging Technologies, Vol. 28, No 3, pp. 441-448, September, 2005.
15. April B. Jacobe, Pinky B. Lomibao, John Jackson, “Board Level Reliability of Wafer Level Chip Scale Packages With Copper Post Technology,” International Electronic Manufacturing Technology, pp. 155-161, Putrajaya, Malaysia 2006.
16. Ahmer Syed,” Updated Life Prediction Models for Solder Joints with Removal of Modeling Assumptions and Effect of Constitutive Equations,”7th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE pp. 1-9, 2006.
17. Wiese, S.,et al, “Microstructural Dependendence ofConstitutive Properties of Eutectic SnAg and SnAgCuSolders,” 53rd Electronic Components and Technology Conference, pp. 197-206, 2003.
18. Schuber A, ”Fatigue Life Models for SnAgCu and SnPb Solder Joints Evaluated byExperiments and Simulation,”IEEE Electronic Components and Technology Conference, pp. 603-610, 2003.
19. A. Schubert, R. Dudek, H. Walter, E. Jung, A. Gollhardt, B. Michel, H. Reichl, “Reliability Assessment of Flip-Chip Assemblies with Lead-free Solder Joints,” IEEE Electronic Components and Technology Conference, pp.1246-1255, 2002
20. Dudek, R., Nylen, M., Schubert, A., Michel, B., Reichl,H., “An Efficient Approach to Predict Solder Fatigue Lifeand its Application to SM-and Area Array Components,”47IhECTC Electronics Components &;Technology Conference,San Jose, CA, USA, May 21-24, pp. 462-471, 1997.
21. Bret A. Zahn, “Solder Joint Fatigue Life Model Methodology for 63Su37Pb and 95.SSn4AgO.SCu Materials,” IEEE Electronic Components and Technology Conference, pp,83-94, 2003.
22. Mohammad Motalab, Zijie Cai, Jeffrey C. Suhling, Pradeep Lall, ”Determination of Anand constants for SAC Solders using Stress-Strain or Creep Data,”13th IEEE ITHERM Conference, pp. 910-923, 2012.