臺灣博碩士論文加值系統

本研究目標為利用電鍍製程以析鍍出均勻性佳且鍍層成份為錫鋅共晶(Sn-9Zn)的合金鍍層，以作為錫鋅隆點的銲錫層。
本實驗使用267ml Hull Cell電鍍槽，藉著改變不同的鍍液濃度及電流大小，使用直流電(Direct Current)電源，以找到最接近錫鋅共晶的最佳條件，接著再利用此條件，在體積為1L的錫鋅電鍍液中，進行大面積的電鍍，在此實驗中所使用的電源包括，直流電流及脈衝電流(Pulse Current)，並以上述之最佳條件進行電鍍錫鋅隆點的製程。在本實驗中，利用GDS 縱深分析(GDS Depth Profile)，分析鍍層內元素分佈的均勻性。
由Hull Cell試驗槽的實驗結果發現，當電流密度在0.16A/dm2以上時，所得到的鍍層之錫含量皆少於80wt%，並由實驗結果發現，若欲得到接近錫鋅共晶組成時，則電流密度不可高於0.13A/dm2。以此條件應用於1L的鍍液中進行電鍍時，必須添加Polyethylene glycol(PEG)以消除氫氣附著，但是會影響鍍層內錫與鋅的析出量，並且造成錫與鋅不能同時析出。本實驗進一步採用脈衝電流，如此，則鍍層內之錫與鋅兩元素能同時析出，明顯的改善了鍍層內元素分佈的均勻性。Pulse-off的時間為0.1ms時，則鍍層內之錫與鋅能同時析出，在本實驗中，並藉著改變不同的ZnSO4 ● 7H2O、SnCl2的濃度，及Pulse-off的時間，以求得到均勻性佳且鍍層成份為錫鋅共晶的合金鍍層之最佳條件。電鍍層利用DSC測試得熔點為198.84℃，相當接近錫與鋅的共晶成份(Sn-9Zn)。

The goal of this research is to produce uniform Sn-Zn eutectic deposit by electroplating. The deposit is intended to apply for Pb-free solder bump.
The best electroplating condition was established by manipulating the concentration and current density with 267ml Hull Cell. The condition was then applied for the plating experiment in a 1L plating bath. The plating current applied in this research includes direct current and pulse current.
The results of Hull Cell experiment showed that the Sn content of the deposit produced at current density above 0.16A/dm2 is less than 80wt%. The current density must be below 0.13A/dm2 to achieve eutectic Sn-Zn composition. PEG(Polyethylene glycol) was added into the plating solution to eliminate the adsorption of H2. PEG affects the deposit composition and was unable to produce simultaneous deposition of Sn and Zn. Pulse current was applied to enhance simultaneous deposition of Sn and Zn. Pulse plating improved the uniformity of Sn and Zn in the deposit. Simultaneous deposition of Sn and Zn was achieved at a pulse-off time of 1ms. The deposit with eutectic composition was characterized with DSC to exhibit a melting temperature of 198.84℃. Both composition and melting temperature confirm that the deposit composition is close to the Sn-Zn eutectic composition.

中文摘要…………………………………………………І
英文摘要…………………………………………………Ⅱ
總目錄……………………………………………………Ⅲ
表目錄……………………………………………………Ⅵ
圖目錄……………………………………………………Ⅶ
第一章 簡介…………………………………………… 1
1-1電子構裝技術……………………………………… 1
1-1-1 覆晶技術發展趨勢…………………………… 1
1-1-2 無鉛銲錫……………………………………… 5
1-2電鍍理論…………………………………………… 6
1-2-1 電鍍熱力學…………………………………… 6
1-2-2 電鍍動力學…………………………………… 13
1-2-3 脈衝電鍍(Pulse Plating)……………………17
1-3 電鍍錫鋅合金…………………………………20
1-4 實驗目的…………………………………………21
第二章 實驗方法與步驟……………………………22
2-1實驗構想…………………………………………22
2-2使用267ml Hull Cell試驗槽析鍍錫鋅鍍層…22
2-2-1 實驗設備……………………………………22
2-2-2 電鍍液組成…………………………………24
2-2-3 底材前處理…………………………………24
2-2-4 電鍍操作……………………………………28
2-2-5 電流密度換算………………………………30
2-2-6 鍍層成份分析………………………………30
2-3大面積電鍍……………………………………30
2-3-1 實驗設備……………………………………30
2-3-2 電鍍液組成…………………………………32
2-3-3 底材前處理…………………………………32
2-3-4 電鍍操作……………………………………32
2-3-5 鍍層成份分析………………………………35
2-3-6 鍍層元素縱深分析…………………………35
2-3-7 鍍層示差掃描熱量分析……………………37
第三章 結果與討論………………………………38
3-1 Hull Cell直流電鍍的析鍍行為……………38
3-2直流電源大面積電鍍…………………………43
3-2-1 析鍍行為…………………………………43
3-2-2 PEG(Polyethylene glycol)對析鍍行為的影響…43
3-3直流電電鍍所得鍍層成份之均勻性…………47
3-4脈衝電流電鍍鍍層之成份均勻性……………57
3-4-1 峰值電流0.1A的鍍層……………………58
3-4-2 峰值電流0.3A的鍍層……………………61
3-4-3 不同Pulse-off時間之析鍍行為………66
3-4-4 鍍層之熔點分析…………………………71
3-4-5 Pulse-off時間對鍍層表面型態之影響…73
第四章 結論………………………………………75
參考文獻……………………………………………76
致謝…………………………………………………81
自述…………………………………………………82

1.J. H. Lau, “Electronic Packaging： Design, Materials, Process and Reliability”, McGraw-Hill, New York, 1998, Chapter 1.
2.D. P. Seraphim, R. C. Lasky and C. Y. Li, “Principles of Electronic Packaging”, McGraw-Hill, New York, 1989, Chapter 1.
3.呂宗興, “電子構裝技術的發展歷程”, 工業材料115期, 1996, pp.49~53.
4.陳玄芳, “覆晶式封裝的技術與應用”, 機械工業233期, 2000, pp. 10~25.
5.楊省樞, “覆晶新組裝技術”, 工業材料163期, 2000, pp.162~167.
6.林光隆, “多晶片模組電子構裝製程技術：子計劃-電子構裝基板金屬化及銲錫隆點製程技術(I)：氧化鋁基板”, 國科會研究計劃, 民國83年.
7.許坤賜, “電鍍參數對銲錫隆點均勻性影響及可靠度性質分析”, 國立成功大學碩士論文, 民國88年.
8.J. H. Lau, “Flip Chip Technologies”, McGraw-Hill, New York, 1996, Chapter 3.
9.孔令臣, “覆晶凸塊技術”, 工業材料139期, 1998, pp.155~161.
10.J. Vardaman, “Surface Mount Technology：Recent Japanese Developments”, IEEE Press, Part 4, New York, 1993, pp214~230.
11.J. H. Lau, “Chip on Board Technologies for Multichip Modules”, Van Nostrand Reinhold, An International Thomson Publishing Company, New York, 1994, Chapter 5.
12.D. S. Patterson, P. Elenius and J. A. Leal, “Wafer Bumping Technologies-A Comparative Analysis of Solder Deposition Processes and Assembly Considerations”, Advances in Electronic Packaging-1997, Vol. 1, ASME, 1997, pp.337~351.
13.S. Tonapi, “Reliability of Lead-Free Solder Interconnects-A Review”, 2002 Proceeding Annual Realiability and Maintainability Symposium, 2002, pp. 423~428.
14.侯振祺, “Si/Ta/TaCu/Cu/Ni-P/Sn-Pb銲錫隆點之製作與可靠度研究”, 國立成功大學碩士論文, 民國90年.
15.溫英男, “錫鉛凸塊技術與覆晶技術之應用”, 電子月刊第六卷第十一期, 民國89年11月, pp. 178~185.
16.G. A. Rinne, “Solder Bumping Method for Flip Chip Packaging”, 1997 Electronic Components and Technology Conference, Proceedings 47th, IEEE, San Jose, CA, USA, May 1997, pp. 240~247.
17.K. Seyama, H. Yamamoto, K. Satou, H. Yoshimuea, H. Ota and Y. Usui, “Transcription Solder Bump Technology Using the Evaporation Method”, 1998 International Conference on Multichip Modules and High Density Packaging, IEEE, Denver, Colorado, April 1998, pp. 314~318.
18.C. L. Wong and J. How, “Low Cost Flip Chip Bumping Technologies”, 1997 IEEE/CMPT Electronic Packaging Technology Conference, IEEE, Singapore, October 1997, pp. 244~245.
19.L. Li, S. Wiegele, P. Thompson and R. Lee, “Stencil Printing Process Development for Low Cost Flip Chip Interconnect”, 1998 Electronic Components and Technology Conference, Proceedings 48th, IEEE, Seattle, Washington, USA, May 1998, pp. 421~426.
20.P. Elenius, “Flex on Cap – Solder Paste Bumping”, 1997 Electronic Components and Technology Conference, Proceedings 47th, IEEE, San Jose, CA, USA, May 1997, pp. 248~253.
21.E. Jung, J. Kloeser, J. Nave, G. Englmann, and L. Dietrich, “Reliability Investigations of Different Bumping Process for Flip Chip and TAB Application”, 1996 IEEE/CMPT International Electronics Manufacturing Symposium, IEEE, Austin, Texas, USA, October 1996, pp. 274~281.
22.T. D. Dudderar, Y. Degani, J. G. Spadafora, K. L. Tai and R. C. Frye, “AT＆T Surface Mount Assembly：A New Technology for the Large Volume Fabrication of Cost Effective Flip-Chip MCMs”, The International Journal of Microcircuits and Electronic Packaging, Vol. 17, No. 4, 1994, pp. 361~368.
23.H. Noro, S. Ito, M. Kuwamura and M. Mizutani, “A Study of New Flip Chip Packaging Process for Diversified Bump and Land Combination”, 1998 IEMT/IMC Proceedings, IEEE, Tokyo, Japan, April 1998, pp. 100~105.
24.鍾明錦, “以錫膏印製Ta/CuTa/Cu/Ni/Au/Sn-Pb銲錫隆點及其可靠度之研究”, 國立成功大學碩士論文, 民國90年.
25.H. Ezawa, M. Miyata, S. Honma, H. Inoue, T. Tokuoka, J. Yoshioka and M. Tsujimura, “Eutectic Sn-Ag Solder Bump for ULSI Flip Chip Technology”, 2000 Electronic Components and Technology Conference, Proceedings. 50th, IEEE, Las Vegas, NV, USA, pp. 1095~1100.
26.G. A. Selivanova, K. M. Tyutina and V. A. Kudryavtsvea, “Tin-Zinc Electroplating of Parts for Soldering from Acid Bath”, Protection of Metals, Vol.35, No. 5, 1999, pp. 511~512.
27.賴玄金, “從IPC Work’99會議看無鉛銲錫電子構裝之應用現況與發展趨勢”, 工業材料158期, 2000, pp. 99~107.
28.謝哲松, “無鉛銲錫對我電子產業之衝擊”, 化工資訊61期, 2000年12月, pp. 61~66.
29.P. A. Magill, C. Rinne and P. A. Deane, “Electroplating Lead Free Solders for Flip Chip Packaging”, Advanced Packaging , November 2000, pp. 14~15.
30.林西音編著, “金屬電鍍學”, 五洲出版社印行, 民國69年, p. 259.
31.余鐵城編著, “表面處理”, 全華科技圖書股份有限公司印行, 民國78年8月, Chapter 2.
32.M. Paunovic and M. Schlesinger, “Fundamentals of Electrochemical Deposition”, John Wiley＆Sons, New York, 1998, Chapter 11.
33.陳佳伶, “以電解沉積法製備碲化鋅之研究”, 國立成功大學碩士論文, 民國87年, pp. 22~25.
34.W. Blum and G. B. Hogaboom, “Principles of Electroplating and Electroforming”, McGraw-Hill, 1949, third Edition, Chapter 22.
35.M. Pourbaix, “Altas of Electrochemical Equilibrium in Aqueous Solution”, NACE, Houston, 1974, pp. 406~413 and 475~484.
36.F. A. Lowenheim, “Electroplating”, McGraw-Hill, New York, 1986, Chapter 8 and 16.
37.N. Ibl, “Some Theoretical Aspects of Pulse Electrolysis”, Surface Technology, Vol 10, 1980, pp. 81~104.
38.N. V. Mandich, “Pulse and Pulse-Reverse Electroplating”, Metal Finishing, Vol. 98, Issue 1, 2000, pp. 375~380.
39.L. J. Durney, “Electroplating Engineering Handbook”, 1984, fourth edition, Chapter 31.
40.J. C. Puipple and F. Leaman, “Theory and Practice of Pulse Plating”, published by American Electroplaters and Surface Finishers Society, 1986, Chapter 3.
41.S. J. Blunden, “Sn-Zn Alloy Electroplates Outperform Cadmium Deposits”, Advanced Materials＆Processes, December 1991, pp. 37~39.
42.G. E. Shahin, “Alloys Are Promising as Chromium or Cadimum Substitutes”, Plating＆Surface Finishing, August 1998, pp. 12~13.
43.陳宏澤, “錫鋅合金電鍍技術”, 工業技術第48期, 民國68年2月, pp. 32~36.
44.J. Rasmussen, “Tin/Zinc Alloy Plating”, Plating＆Surface Finishing, February 2001, pp. 18~20.
45.O. A. Ashiru and J. Shirokoff, “Electrodeposition and Characterization of Tin-Zinc Alloy Coatings”, Applied Surface Science 103, 1996, pp. 159~169.
46.V. S. Vasantha, M. Pushpavanam, P. Kamaraj and V. S. Muralidharan, “Role of Peptone in the Electrodeposition of Tin and Tin-Zinc Alloys from Neutral Gluconate Bath”, Transaction of Institute Metal Finishing, Vol. 74, No. 1, January 1996, pp. 28-32.
47.M. An, Y. Zhang, J. Zhang, Z. Yang and Z.Tu, “Mechanism of Additives in Electroplating of Sn-Zn Alloy”, Plating&Surface Finishing, May 1999, pp.130~132.
48.文生譯, “哈式槽試驗(上)”, 金屬表面技術雜誌第85期, pp. 36~39.
49.雍知盛, “何式槽電鍍試驗,” 民國73年2月, Chapter 2,3,4.
50.儀器總覽5, “材料分析儀器”, 國科會精儀中心編印, 民國87年, pp. 78~81.
51.儀器總覽5, “材料分析儀器”, 國科會精儀中心編印, 民國87年, pp. 136~137.
52.T. B. Massalski, “Binary Alloy Phase Diagrams”, Vol. 2, 1986, p. 2086.
53.F. A. Lowenheim, “Modern Electroplating”, 1978, third edition, Chapter 18.
54.北原文雄等編著, “界面活性劑應用實務”, 復漢出版社印製, 民國79年, pp. 85~87.
55.C. M. A. Brett and A. M. O. Brett, “Electrochemistry Principles, Methods, and Applications”, Oxford University Press, 1993, Chapter 2 and 3.