臺灣博碩士論文加值系統

本研究提出一種低功率消耗之互補式金氧半運算放大器。設計時採用軌對軌輸入級來增加輸入共模電壓的範圍，疊接組態用於提高放大器增益。AB類輸出級設計使得輸出電壓可以到達電源電壓範圍，並以操作在弱反轉區的偏壓設計達到低電流損耗之目的。包含啟動電路之偏壓電路設計用於提供運算放大器所需之穩定偏壓電流，以建立與供應電源無關之直流操作點。除了低功率消耗的優點之外，本運算放大器同時具有很高的共模拒斥比，電源拒斥比以及很小的晶片面積0.015 mm2。
為了得到最佳的運算放大器性能，電路佈局上的主要原則包括運用同心圓架構和假元件以降低製程不匹配的影響，以及應用保護環於差動輸入對、補償電容和複晶電阻以阻隔來自基體與電源的雜訊。電路設計時亦考慮因製程變化所引起的元件參數飄移之影響，進行最壞情況模擬，以確認所有電路性能均能夠符合設計需求。整個運算放大器的設計流程採用全客戶設計方式，電路製作使用0.5微米、二層複晶矽二層金屬、N型井、標準互補式金屬氧化物半導體製程。
在論文中亦介紹了幾種運算放大器量測的方法，對測試晶片實際進行量測驗證，並與模擬結果作比較。實驗證明運算放大器共模拒斥比達78 dB以上，電源拒斥比達75 dB以上，輸入偏移電壓在 ± 3.1 mV以內，操作於3.3 V電源電壓時其功率消耗小於50 μW。晶片面積很小以及低功率消耗的特性，使得本論文所提出之運算放大器非常適合於可攜式產品之應用。

This study presents a low-power CMOS operational amplifier (OP). The rail-to- rail input stages are used to increase the range of input common-mode voltage and the cascode architecture is utilized to increase the gain of the amplifier. The rail-to-rail output voltage can be achieved using the class-AB output stages, and the current consumption of this OP is minimized using the weak-inversion biasing design. A bias circuit including a start-up circuitry is designed to provide a stable bias current for the OP to build up the operating points that are insensitive to supply voltages. Besides the advantage of low-power consumption, this OP has a high common-mode rejection ratio (CMRR), a high power-supply rejection ratio (PSRR) and a small chip area of 0.015 mm2.
To achieve a high-performance OP, the common-centroid layout and dummy devices are implemented to reduce the mismatch due to the process variation, as well as the guard ring for differential input pairs, compensation capacitors and poly resistors to prevent the noise coupling from substrate or supply voltage. The deviation of the device parameter due to process variation has been simulated in the worst case to identify all the circuit performance to meet the design criterion. The OP is designed using the full-custom procedure, and is fabricated using the standard CMOS technology of 0.5-μm double-poly double-metal N-well process.
Several measuring configurations are described in this thesis to verify the performance of the test chip. The difference between measurement and simulation are compared. Experimental results indicate that the designed OP realizes a CMRR of greater than 78 dB, a PSRR of greater than 75 dB, an input offset voltage of less than ± 3.1 mV and a power consumption of less than 50 μW at a supply voltage of 3.3 V. with the characteristics of small chip area and low-power consumption, this proposed OP is well suitable for the applications of portable products.

中文摘要…………………………………………………………………………..i
英文摘要…………………………………………………………………………..ii
誌謝…………………………………………………………………………….…iii
目錄…………………………………………………………………………….…iv
圖目錄………………………………………………………………………….…vi
表目錄……………………………………………………………………………viii
第一章 緒論……..………………………………………………………………..1
1-1 研究背景…...…………………………………………………………...1
1-2 研究動機與目的………………………………………………………..1
1-3 論文架構及研究方法…………………………………………………..2
第二章 低功率運算放大器設計…………………………………………………4
2-1 弱反轉區………………………………………………………………...4
2-2 帶參考電路……………………………………………………………...5
2-2.1 負TC電壓……………………………………………………….7
2-2.2 正TC電壓……………………………………………………….8
2-2.3 帶參考電路實現………………………………………………....9
2-3 軌對軌輸入電路分析…………………………………………………..10
2-4 起始電路………………………………………………………………..12
2-5 雙級運算放大器之補償……………………………………………..…13
2-6 軌對軌輸出級電路分析…………………………………………….….14
2-7低功率運算放大器電路實現…………………………………………...16
2-8 佈局及佈局考量………………………………………………………..17
第三章 低功率運算放大器電路模擬結果………………………………………21
3-1共模拒斥比.……………………………………………………………...21
3-2電流消耗 ………………………………………………………………22
3-3直流增益.……………………………………………………….………..23
3-4相位邊限.………………………………………………………….……..24
3-5負電源拒斥比.……………………………………………………….…..25
3-6正電源拒斥比.……………………………………………….…………..26
3-7輸入共模電壓範圍.………………………………….…………………..27
3-8 雜訊.……………………………………………………………………..29
3-9單位增益頻寬 .……………………………………………..…………...30
3-10 設定時間 .……………………………………………………………..31
3-11 規格與模擬結果………………………………………..……………...33
第四章 量測方法及步驟介紹………………………….…………………………34
4-1輸入偏移電壓……………………………………..……………………...34
4-2開迴路增益………………………………………………………………34
4-3共模輸入增益……………………………………………………………35
4-4等效輸入電阻 ……………………………………………………..……35
4-5等效輸出電阻……………………………………………………………35
4-6增益頻寬積………………………………………………………………36
4-7設定時間 …………………………………………………………….…36
4-8迴轉率…………………………………………………………………...37
4-9共模拒斥比……………………………………………………………...37
4-10電源拒斥比………………………………………………….…………38
4-11雜訊……………………………………………………………….……39
第五章 量測結果與模擬結果比較…………………………………………..….40
5-1量測結果……………………………………………………………..…40
5-1.1上升時間.………………………………………………………40
5-1.2下降時間.………………………………………………………40
5-1.3設定時間.………………………………………………………41
5-1.4雜訊.……………………………………………………………42
5-1.4偏移電壓.………………………………………………………42
5-2量測結果與模擬結果比較表……………………………….………….43
第六章 結論與展望……………………………………………………………..44
6-1結論……………………………………………….…………………….44
6-2展望……………………………………………………………………. 44
附錄I 下線晶片DIE PHOTO………………………………………….……. 46
參考文獻..…….…………………………………………………………….…….47

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