臺灣博碩士論文加值系統

以放大器為基準(amplifier-based)的類比數位轉換器(analog-to-digital converter, ADC),例如流水線式(pipelined)、循環式(cyclic)、或兩階式(two-step)可運用於每秒取樣數從數百萬次至一億次甚至更高,解析度則位於8位元至16位元之間的應用。然而當CMOS製程微縮時，電路供電電壓(supply voltage)和電晶體的本質增益(intrinsic gain)都跟著降低，因此ADC的擺幅和放大器的實現都受到了限制。雖然之前文獻提出的使用開迴路放大器架構(open-loop architecture) 配合類比或數位校正可以讓amplifier-based ADC實現於CMOS先進製程。然而隨著CMOS製程持續微縮，對於open-loop architecture來說，開迴路放大器的非線性問題將會越來越嚴重，因此設計將會需要複雜的非線性校正。同時，隨著電壓擺幅的降低，傳統電壓領域ADC的解析度也受到了限制。為了解決上述的問題，使用時間領域之類比數位轉換器架構(time-domain ADC, TADC)被提出於此研究中。因為隨著製程微縮，數位電路的功耗會降低，而時間訊號的解析度會提升，所以此架構實現於先進製程時將會有好的轉換效率。而且因為時間領域訊號的範圍並不會隨著supply voltage降低而減少，開迴路放大器的非線性問題也可以因此減輕。
在此研究中包含兩個積體電路設計雛型。在第二章中，第一個設計是一個解析度12位元，每秒取樣三百四十萬次的兩階段循環式TADC，實現於0.18微米CMOS製程。此TADC在不使用任何高增益放大器的情況下，藉著電壓時間轉換器(voltage-to-time converter, VTC)與一個12dB增益的放大器，和一個時間放大器(TA)來實現殘餘放大器的功能，以達到12位元的解析度。另外，此TADC也不需要非線性校正和製程變異追蹤電路。每個子電路架構的雜訊分析也在此章中呈現。為了要進一步驗證雜訊分析，另一個具有不同元件尺寸的對照組TADC也有實際下線，進而比較兩個TADC的訊號對雜訊比(SNR)和訊號對雜訊加失真比(SNDR)。
在第三章中，第二個設計是一個解析度10位元，每秒取樣四千萬次的兩階段TADC，實現於0.18微米CMOS製程。第二個設計改良了第一個設計的取樣速度，同時也完全不使用任何增益放大器。和第一個設計一樣，此架構也不需要非線性校正和製程變異追蹤電路。由於此TADC不需要非線性校正電路，運用在此設計的背景數位校正的硬體複雜度可因此大量降低。因此，此TADC所需的數位校正收斂周期只需622個，比之前使用電壓領域的背景數位校正ADC少了十倍以上。

The amplifier-based analog-to-digital converter (ADCs), such as pipelined, cyclic, and two-step architecture, are a suitable candidate for sampling rates from a few mega samples per second (MSPS) up to 100MSPS or even above, and resolutions range from 8 bits to 16 bits. However, as CMOS technology continues to shrink, the decreased supply voltage would limit the swing of the ADC, and the reduced intrinsic gain of the transistors would make the conventional operational amplifier difficult to realize. Although the early proposed open-loop architectures with the analog/digital calibration can be implemented in an advanced CMOS process, the amplifier non-linearity issue would become more severe as CMOS technology continues to scale down. A sophisticated non-linear calibration would be required and complicates the design. In addition, as the voltage swing decreases, the resolution of the conventional voltage-domain ADCs are also limited as well. To solve the issue described above, a time-domain ADC (TADC) architecture is proposed in this thesis. Since the power consumption of the digital circuit decreases, and the resolution of a time-domain signal is improved with the technology scaling, the TADC becomes a candidate for the power efficient architecture in the advanced process. Also, since the time-domain signal range would not be limited by the decreased supply voltage, the non-linearity issue in the TADC architecture could be relieved.
Two prototype ICs were designed during this research. In chapter 2, the first design is a 12-bit 3.4MS/s two-step cyclic TADC implemented in a 0.18um CMOS process. The proposed TADC uses a voltage-to-time converter (VTC) with a 12dB gain amplifier and the proposed time amplifier (TA) as residue amplifiers to achieve 12-bit resolution without high gain amplifiers. In addition, non-linear calibration, and the process variation tracking blocks are also not required. The noise analysis for each TADC building block is also presented in this chapter. To verify the noise analysis further, another TADC is fabricated with different devices sizes, in order to compare the measured signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR).
In chapter 3, the second design is a 10-bit 40MS/s two-step TADC implemented in a 0.18um CMOS process. The second design is realized to improve the sampling rate of the first design, and also to eliminate the use of the amplifiers. Same as the first design, non-linear calibration, and the process variation tracking blocks are also not required. Since the TADC can operate without the non-linear calibration, the hardware complexity of the digital background calibration adopted in this work can be greatly reduced. Therefore, the calibration time of the TADC requires only 622 clock cycles, which is over 10 times less than prior voltage-domain digitally-calibrated ADCs.

1. Introduction 1
1.1 Overview 2
1.2 Amplifier-Based ADCs 3
1.3 Amplifier-Based ADC Design Difficulties in Advanced Technology 4
1.4 Previous Published Time-Domain ADCs 5
1.5 Proposed Time-Domain Amplifier-Based ADC 7
1.6 Thesis Organization 8

2. A 12-bit 3.4MS/s Two-Step Cyclic Time-Domain ADC in 0.18μm CMOS 9
2.1 Motivation 10
2.2 Circuit Architecture 12
2.2.1 Circuit Description 13
2.2.2 4.5-bit VTMDAC 15
2.2.3 4.5-bit CADC 18
2.2.4 2.5-bit Sub-TDC 19
2.2.5 2.5-bit Sub-DTC with a Time Subtractor and Delay Stage 20
2.3 Circuit Non-idealities 23
2.3.1 Gain Inaccuracy 24
2.3.2 Non-linearity 26
2.3.3 TA Input Range Limitation 29
2.3.4 Mismatch Effect 32
2.3.5 Comparator Non-zero Delay 34
2.4 Noise Analysis 35
2.4.1 VTC Noise Analysis 35
2.4.2 VTMDAC Noise Analysis 43
2.4.3 TA Noise Analysis 46
2.4.4 TADC SNR 47
2.5 Measurement Setup and Experimental Results 50
2.5.1 Measurement Setup 50
2.5.2 Experimental Results 51
2.5.3 Chip Photo and Performance Summary 55

3. A 10-bit 40MS/s Time-Domain Two-Step ADC with Short Calibration Time 59
3.1 Motivation 60
3.2 Introduction of Different Digital Background Calibration Techniques 61
3.3 Two-step ADC Architecture for Short Calibration Time 65
3.4 Circuit Description 66
3.4.1 Architecture Description 67
3.4.2 Coarse ADC (CADC) and Its Calibration Phase 68
3.4.3 Voltage-to-Time Converter (V/T) and Digital-to-Time Converter (DTC) 69
3.4.4 V/T and DTC Calibration Phases 71
3.4.5 Coarse DAC (CDAC) With Offset ∆a 76
3.4.6 6-bit Fine TDC (FTDC) 80
3.5 Measurement Setup and Experimental Results 82
3.5.1 Measurement Setup 82
3.5.2 Chip Photo and Experimental Results 84
3.6 Conclusion 88

4. Conclusion and Future Work 91
4.1 Conclusion 92
4.2 Future Work 93

Bibliography 96

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