臺灣博碩士論文加值系統

當技術節點在次16奈米以下的時候，結構微縮的工作變得越來越麻煩。平面式電晶體已無法滿足多樣化資通訊晶片使用上的需求。因此，多閘極結構被提出來改善目前的情況。其中，全閘極奈米線場效應電晶體是最受人矚目的結構。此外，擾動的問題也變得益發重要。製程變異、隨機摻雜擾動和隨機功函數擾動是較主要的擾動源。在此篇論文內使用經由全量子力學理論與實驗校估過的三維度量子修正元件模擬技術來探討本質參數擾動對10奈米全閘極奈米線場效應電晶體的影響。對隨機摻雜擾動的部分，從源/汲極延伸處而來的摻雜形成不可忽略的擾動源。當通道摻雜濃度下降時，它的影響會更加巨大，所以研究上也必須把它加進來討論。研究發現臨界電壓擾動的最大值發生在多數摻雜聚集在傳導能帶圖最高點的位置，而且這個現象不受隨機摻雜擾動機制的影響

在製程變異的部分，本研究探討了閘極長度、理想圓柱形元件的半徑、非完美橢圓結構中長短軸縱橫比及氧化層厚度的變異。結果顯示出氧化層厚度的變異小到可以忽略，而理想圓柱形元件的半徑及非完美橢圓結構中長短軸縱橫比對元件的影響最大。本研究透過一個轉換公式連結這兩個元件參數。雖然擁有大縱橫比的元件有較差的短通道參數，卻有較好的製程變異抑制能力。研究隨機摻雜擾動和製程變異一起的影響，發現小縱橫比的元件有較小的擾動，因為它有較小的有效半徑，使它有更好的通道控制能力。

在隨機功函數擾動的部分，擾動主要是由高功函數金屬晶粒的數量及位置所影響。越多的高功函數金屬粒聚集在靠近源極處，元件特性將會退化地更嚴重。製造出擁有遠小於閘極面積金屬粒的閘極可有效減少擾動對元件的影響。與三閘極場效應電晶體相比之下，全閘極奈米線場效應電晶體對擾動問題擁有更佳的抑制能力。若同時考慮隨機功函數擾動及製程變異，擁有小縱橫比的元件受到更嚴重的擾動，這跟隨機摻雜擾動所表現出來的趨勢不一樣。

總之，本研究探討了幾個重要的擾動源對全閘極奈米線場效應電晶體的影響。研究成果可提供給半導體工業界去研發更先進的元件結構、材料與製程技術來提昇晶片的性能。

As the technology node extends to sub-16 nm, the task of device scaling is getting more troublesome. Planar MOSFET could not satisfy the demand of performance. Hence, new structure such as multi-gate structure are proposed. Gate-all-around nanowire (GAA NW) MOSFET device is one of the most attractive structures. Besides, variability problems are becoming so crucial that they degrade the devices’ characteristic as well. Process variation effect (PVE), random dopant fluctuation (RDF) and work function fluctuation (WKF) are major fluctuation sources of all. In this thesis, exploring the influence of intrinsic characteristic fluctuation on GAA NW MOSFET with 10-nm-gate-length is conducted by full quantum mechanics theory and experimentally calibrated 3D quantum corrected device simulation.
In the part of RDF, dopants penetrating from source/drain extension forms another unignorable fluctuation, which becomes more significant as the channel doping concentration decreases, so it must be included. The results show that the largest deviation of Vth is occurred as dopants are flocked at the place corresponding to the peak of conduction band profile regardless of RDF mechanism.
In the part of PVE, the variations of gate length, radius, aspect ratio (AR) and oxide thickness are investigated. The results reveal that the fluctuation of oxide thickness is so small that it can be neglected, and the radius as well as aspect ratio (AR) have influential impact among all PVE factors. They have dependence on each other through a transformation formula. Although the device with large AR has poor SCE parameters, it has better suppression on PVE. Then RDF and PVE are combined to discuss the total impact. Small AR device has minimal fluctuation due to its own small effective radius, resulting in better channel controllability.
In the part of WKF, the fluctuation is induced by the number and the location of metal grain with high work-function. The more metal grain with high work-function gathers near source side, the worse device’s characteristic is. Fabricating the size of metal grain which is far less than gate area can effectively reduce the characteristic fluctuation on device. Compared to tri-gate MOSFET, GAA NW MOSFET has great immunity to variation problems. As WKF and PVE are considered simultaneously, the device with small AR suffers more serious fluctuation, which is different from the trend of RDF.
In summary, this thesis has discussed the impact of most important fluctuation sources on GAA NW MOSFET device. It provides semiconductor industry to develop some advanced device structures, materials and process technologies to promote the performance of chips.

Abstract (Chinese) i
Abstract iii
Acknowledgement v
Contents vi
List of Figures ix
List of Tables xxiii
1 Introduction 1
1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Outline of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 GAA NW MOSFET Devices and Simulation Methodology 9
2.1 Nonideal Channel Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Transport Equations and Physical Models . . . . . . . . . . . . . . . . . 10
vi2.2.1 Quantum-Mechanically Corrected Transport Equations . . . . . . 12
2.2.2 Mobility Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3 Validation between DG+DD Model and NEGF Argument . . . . 22
2.2.4 Calibration between Simulation Result and Experimental Data of
Fabricated Sample . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3 The Statistical Device Simulation . . . . . . . . . . . . . . . . . . . . . . 36
2.3.1 Simulation Technique of Process Variation Effect . . . . . . . . . 37
2.3.2 Simulation Approach of Random Work Function . . . . . . . . . 38
2.3.3 Simulation Method of Random Dopant Fluctuation . . . . . . . . 39
2.4 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3 Process Variation Effects 46
3.1 Magnitude of Gate Length, Radius and Oxide Thickness' Variations . . . 47
3.1.1 The Impact of The Gate Length's Fluctuation . . . . . . . . . . . 47
3.1.2 The Impact of The Radius's Fluctuation . . . . . . . . . . . . . . 50
3.1.3 The Impact of The Oxide Thickness's Fluctuation . . . . . . . . . 53
3.2 Magnitude of Aspect Ratio's Variation . . . . . . . . . . . . . . . . . . . 56
3.2.1 The Impact of The Aspect Ratio's Variation . . . . . . . . . . . . 56
3.2.2 Comparison among Four PVEs . . . . . . . . . . . . . . . . . . . 63
3.3 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4 Random Dopant Fluctuation 65
4.1 RDs in the Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.2 RDs Coming from Source/Drain Extension . . . . . . . . . . . . . . . . . 73
vii4.3 Combination of Different RDs Mechanisms . . . . . . . . . . . . . . . . . 78
4.4 Combined Fluctuation of RDF and PVE . . . . . . . . . . . . . . . . . . 84
4.5 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5 Random Work Function Effects 88
5.1 Work Function Effect on Nanowire . . . . . . . . . . . . . . . . . . . . . 88
5.2 Combined Fluctuation of WKF and PVE . . . . . . . . . . . . . . . . . . 97
5.3 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6 Conclusions and Future Work 101
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Appendix A: Flowchart of NEGF Simulation 122
VITA 123

[1] K. J. Kuhn, M. Y. Liu, and H. Kennel, "Technology Options for 22nm and Beyond,"
in International Workshop on Junction Technology (IWJT), May 2010, pp. 1-6.
[2] K. J. Kuhn, "Considerations for Ultimate CMOS Scaling," IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813-1828, July 2012.
[3] K. J. Kuhn, "CMOS Scaling for the 22nm Node and Beyond: Device Physics
and Technology," in International Symposium on VLSI Technology, Systems and
Applications (VLSI-TSA), April 2011, pp. 1-2.
[4] Jess A. del Alamo, "Nanometre-scale electronics with IIIV compound semiconduc-
tors," Nature, vol. 479, pp. 317-323, Nov. 2011.
[5] J. A. del Alamo, D. Antoniadis, A. Guo, D. -H. Kim, T. -W. Kim, J. Lin, W. Lu, A.
Vardi, and X. Zhao, "InGaAs MOSFETs for CMOS: Recent Advances in Process
Technology," in 2013 IEEE International Electron Devices Meeting (IEDM), Dec.
2013, pp. 24-27.
[6] J. -P. Colinge, "Multiple-gate SOI MOSFETs," Solid-State Electronics, vol. 48, no.
6, pp. 897-905, June 2004.
[7] J. -P. Colinge, "Multiple-gate SOI MOSFETs," Microelectronic Engineering, vol.
84, no. 9-10, pp. 2071-2076, Sept.-Oct. 2007.
[8] T. Sekigawa, and Y. Hayashi, "Calculated threshold-voltage characteristics of an
XMOS transistor having an additional bottom gate," Solid-State Electronics, vol.
27, no. 8, pp. 827-828, 1984.
[9] H. -S. P. Wong, D. J. Frank, and P. M. Solomon, "Device Design Considerations
for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SO1 MOSFET's at
the 25 nm Channel Length Generation," in International Electron Devices Meeting
(IEDM 98), Dec. 1998, pp. 407-410.
[10] T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, T. Ernst, B. Previtali, and
S. Deleonibus, "Multiple gate devices : advantages and challenges," Microelectronic
Engineering, vol. 80, pp. 378-385, June 2005.
[11] C. -W. Lee, S. -R. -N. Yun, C. -G. Yu, J. -T. Park, and J. -P. Colinge, "Device
design guidelines for nano-scale MuGFETs," Solid-State Electronics, vol. 51, no. 3,
pp. 505-510, March 2007.
[12] A. Dayal, S. P. Pandey, S. Khandelwal, and S. Akashe, "Multiple Gate Silicon on
Insulator (SOI) MOSFETs: Device Design and Analysis," in Emerging Research
Areas and 2013 International Conference on Microelectronics, Communications and
Renewable Energy (AICERA/ICMiCR), June 2013, pp. 1-6.
[13] J. -P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys,
"SILICON-ON-INSULATOR "GATE- ALL-AROUND DEVICE"," in Interna-
tional Electron Devices Meeting (IEDM 90), Dec. 1990, pp. 595-598.
[14] J. -P. Colinge, "FROM GATE-ALL-AROUND TO NANOWIRE MOSFETS," in
International Semiconductor Conference, CAS 2007, vol. 1, pp. 11-17.
[15] F. -L. Yang, D. -H. Lee, H. -Y. Chen, C. -Y. Chang, S. -D. Liu, C. -C. Huang, T.
-X. Chung, H. -W. Chen, C. -C. Hang, Y. -H. Liu, C. -C. Wu, C. -C. Chen, S. -C.
Chen, Y. -T. Chen, Y. -H. Chen, C. -J. Chen, B. -W. Chan, P. -F. Hsu, J. -H. Shieh,
H. -J. Tao, Y. -C. Yeo, Yiming Li, J. -W. Lee, P. Chen, M. -S. Liang, Chenming
Hu, "5nm-Gate Nanowire FinFET," in 2004 Symposium on VLSI Technology, June
2004, pp. 196-197.
[16] H. Dadgour, K. Endo, V. De, and K. Banerjee, "Modeling and Analysis of Grain-
Orientation Effects in Emerging Metal-Gate Devices and Implications for SRAM
Reliability," in IEEE International Electron Devices Meeting (IEDM), Dec. 2008,
pp. 1-4.
[17] Y. Li, C. -H. Hwang, T. -Y. Li, and M. -H. Han, "Process-Variation Effect, Metal-
Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging
CMOS Technologies," IEEE Transactions on Electron Devices, vol. 57, no. 2, pp.
437-447, Feb. 2010.
[18] Y. Li, C. -H. Hwang, H. -W. Cheng, "Process-variation- and random-dopants-
induced threshold voltage
uctuations in nanoscale planar MOSFET and bulk Fin-
FET devices," Microelectronic Engineering, vol. 86, no. 3, pp. 277-282, 2009.
[19] C. -Y. Chen, Y. -Y. Chen, and Y. Li, "Multi-Fin Bulk FinFET Characteristic
Fluctuation Induced by Process Variation and Random Dopant," in International
Workshop on Computational Electronics (IWCE), June. 2013, pp. 56-57.
[20] Y. Li and C. -H. Hwang, "The effect of the geometry aspect ratio on the silicon
ellipse-shaped surrounding-gate eld-effect transistor and circuit," Semicond. Sci.
Technol., vol. 24, no. 9, 2009.
[21] M. -S. Lee, B. -G. Park, I. H. Cho, and J. -H. Lee, "Characteristics of Elliptical
Gate-All-Around SONOS Nanowire With Effective Circular Radius," IEEE Elec-
tron Device Letters, vol. 33, no. 11, Nov. 2012.
[22] S. Jha, A. Kumar, and S. Kumar, "Impact of Elliptical Cross-Section on Some Elec-
trical Properties of Gate-All-Around MOSFETs," Bonfring International Journal
of Power Systems and Integrated Circuits, vol. 2, no. 3, Dec. 2012.
[23] H. -S. P. Wong, Y. Taur, and D. J. Frank, "Discrete random dopant distribution
effects in nanometer-scale MOSFETs," Microelectronics Reliability, vol. 38, no. 9,
pp.1447-1456, Sep. 1998.
[24] Y. Li, and H. -W. Cheng, "Statistical device simulation of physical and electri-
cal characteristic uctuations in 16-nm-gate high-/metal gate MOSFETs in the
presence of random discrete dopants and random interface traps," Solid-State Elec-
tronics, vol. 77, pp. 12-19, Nov. 2012.
[25] Y. Li, H. -W. Cheng, and Y. -Y. Chiu, "Interface traps and random dopants induced
characteristic uctuations in emerging MOSFETs," Microelectronic Engineering, vol.
88, no. 7, pp. 1269-1271, July 2011.
[26] A. Asenov, "Random Dopant Induced Threshold Voltage Lowering and Fluctua-
tions in Sub-0.1 m MOSFETs: A 3-D Atomistic Simulation Study," IEEE Trans-
actions on Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998.
[27] Y. Li and C. -H. Hwang, "Discrete-dopant-induced characteristic
uctuations in
16nm multiple-gate silicon-on-insulator devices," J. Appl. Phys., vol. 102, no. 8,
2007, 084509.
[28] Y. Li and C. -H. Hwang, "Large-scale atomistic approach to discrete-dopant-
induced characteristic
uctuations in silicon nanowire transistors," Semicond. Sci.
Technol., vol. 205, no. 6, May 2007.
[29] Y. Li, C. -H. Hwang, and T. -Y. Li, "Random-Dopant-Induced Variability in Nano-
CMOS Devices and Digital Circuits," IEEE Transactions on Electron Devices, vol.
56, no. 8, pp. 1588-1597, Aug. 2009.
[30] T. Shinada, M. Hori, Y. Ono, K. Taira, A. Komatsubara, T. Tanii, T. Endoh,
and I. Ohdomari, "Reliable Single Atom Doping and Discrete Dopant Effects on
Transistor Performance," in IEEE International Electron Devices Meeting (IEDM),
Dec. 2010, pp. 592-595.
[31] N. Seoane, A. Martinez, A. R. Brown, J. R. Barker, and A. Asenov, "Current
Variability in Si Nanowire MOSFETs Due to Random Dopants in the Source/Drain
Regions: A Fully 3-D NEGF Simulation Study," IEEE Transactions on Electron
Devices, vol. 56, no. 7, pp. 1388-1395, July 2009.
[32] Y. Kamakura, G. Milnikov, N. Mori, and K. Taniguchi, "Impact of Attractive Ion
in Undoped Channel on Characteristics of Nanoscale Multigate Field Effect Tran-
sistors: A Three-Dimensional Nonequilibrium Greens Function Study," Japanese
Journal of Applied Physics, vol. 49, no. 4S, Feb. 2010, 04DC19.
[33] M. Uematsu, K. M. Itoh, G. Milnikov, H. Minari, and N. Mori, "Simulation of
the Effect of Arsenic Discrete Distribution on Device Characteristics in Silicon
Nanowire Transistors," in IEEE International Electron Devices Meeting (IEDM),
Dec. 2012, pp. 709-712.
[34] H. -W. Cheng, F. -H. Li, M. -H. Han, C. -Y. Yiu, C. -H. Yu, K. -F. Lee, and Y.
Li, "3D Device Simulation of Work Function and Interface Trap Fluctuations on
High- / Metal Gate Devices," in IEEE International Electron Devices Meeting
(IEDM), Dec. 2010, pp. 379-382.
[35] Y. Li, H. -W. Cheng, Y. -Y. Chiu, C. -Y. Yiu, and H. -W. Su, "A Unied 3D Device
Simulation of Random Dopant, Interface Trap and Work Function Fluctuations
on High-/Metal Gate Device," in IEEE International Electron Devices Meeting
(IEDM), Dec. 2011, pp. 107-110.
[36] N. Seoane, G. Indalecio, E. Comesaa, A. J. Garca-Loureiro, M. Aldegunde, and
K. Kalna, "Three-Dimensional Simulations of Random Dopant and Metal-Gate
Workfunction Variability in an In0.53Ga0.47As GAA MOSFET," IEEE Electron
Device Letters, vol. 34, no. 2, pp. 205-207, Feb. 2013.
[37] T. Matsukawa, Y. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O uchi,
W. Mizubayashi, H. Ota, S. Migita, Y. Morita, and M. Masahara, "Inuence of work
function variation of metal gates on uctuation of sub-threshold drain current for n
eld-effect transistors with undoped channels," Japanese Journal of Applied Physics,
vol. 53, no. 4S, Feb. 2014, 04EC11.
[38] Z. Chen, X. Zhou, G. Zhu, and S. Lin , "Interface-Trap Modeling for Silicon-
Nanowire MOSFETs," in IEEE International Reliability Physics Symposium
(IRPS), May 2010, pp. 977-980.
[39] R. Gautam, M. Saxena, R.S. Gupta and M. Gupta, "Impact of Interface Fixed
Charges on the Performance of the Channel Material Engineered Cylindrical
Nanowire MOSFET," International Journal of VLSI design Communication Sys-
tems (VLSICS), vol. 2, no. 3, pp. 225-241, Sept. 2011.
[40] F. Najam, Y. S. Yu, K. H. Cho, K. H. Yeo, D. -W. Kim, J. S. Hwang, S. Kim,
and S. W. Hwang, "Interface Trap Density of Gate-All-Around Silicon Nanowire
Field-Effect Transistors With TiN Gate: Extraction and Compact Model," IEEE
Transactions on Electron Devices, vol. 60, no. 8, pp. 2457-2463, Aug. 2013.
[41] A. Suzuki, T. Kamioka, Y. Kamakura, K. Ohmori, K. Yamada, and T. Watan-
abe, "Source-induced RDF Overwhelms RTN in Nanowire Transistor: Statistical
Analysis with Full Device EMC/MD Simulation Accelerated by GPU Computing,"
in IEEE International Electron Devices Meeting (IEDM), Dec. 2014, pp. 30.1.1 -
30.1.4.
[42] Y. Jiang, T. Y. Liow, N. Singh, L.H. Tan, G. Q. Lo, D. S. H. Chan and D. L. Kwong
, "Performance Breakthrough in 8 nm Gate Length Gate-All-Around Nanowire
Transistors using Metallic Nanowire Contacts," in Symposium on VLSI Technology,
June 2008, pp. 34-35.
[43] K. Tachi, T. Ernst, C. Dupre, A. Hubert, S. Becu, H. Iwai, S. Cristoloveanu and
O. Faynot, "Transport Optimization with Width Dependence of 3D-stacked GAA
Silicon Nanowire FET with High-k/Metal Gate Stack," In Conference in Silicon
Nanoelectronics Workshop, 2009.
[44] S. -D. Yang, J. -S. Oh, H. -J. Yun, K. -S. Jeong, Y. -M. Kim, S. Y. Lee, H. -D. Lee,
and G. -W. Lee, "The Short Channel Effect Immunity of Silicon Nanowire SONOS
Flash Memory Using TCAD Simulation," Transactios on Electrical and Electronic
Materials, vol. 14, no. 3, pp. 139-142, June 2013.
[45] T. Irisawa, M. Oda, K. Ikeda, Y. Moriyama, E. Mieda, W. Jevasuwan, T. Maeda,
O. Ichikawa, T. Osada, M. Hata, Y. Miyamoto and T. Tezuka, "High Electron
Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed
by MOVPE Growth on Narrow Fin Structures," in IEEE International Electron
Devices Meeting (IEDM), Dec. 2013, pp. 2.2.1 - 2.2.4.
[46] J. -S. Lee, Y. -K. Choi, D. Ha, S. Balasubramanian, T. -J. King, and J. Bokor,
"Hydrogen Annealing Effect on DC and Low-Frequency Noise Characteristics in
CMOS FinFETs," IEEE Electron Device Letters, vol. 24, no. 3, pp. 186-188, March
2003.
[47] S. Bangsaruntip, G. M. Cohen, A. Majumdar, Y. Zhang, S. U. Engelmann, N. C.
M. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. Guillorn, T. Barwicz, L.
Sekaric, M. M. Frank, and J. W. Sleight, "High Performance and Highly Uniform
Gate-All-Around Silicon Nanowire MOSFETs with Wire Size Dependent Scaling,"
in IEEE International Electron Devices Meeting (IEDM), Dec. 2009, pp. 297-300.
[48] M. G. Ancona, "Density-gradient theory: a macroscopic approach to quantum
connement and tunneling in semiconductor devices," J. Comp. Elect., vol. 10, no.
1-2, pp. 65-97, June 2011.
[49] T.-W. Tang, X. Wang, and Y. Li, "Discretization scheme for the density-gradient
equation and effect of boundary conditions," J. Comp. Elect., vol. 1, pp.389-393,
2002.
[50] S. Odanaka, "Multidimensional discretization of the stationary quantum drift-
diffusion model for ultrasmall MOSFET structures," IEEE Trans. Comput. Aided
Des. Integr. Circuits Syst., vol. 23, no. 6, pp.837-842, June 2004.
[51] G. Roy, A. R. Brown, A. Asenov and S. Roy, "Quantum Aspects of Resolving Dis-
crete Charges in Atomistic Device Simulations," Journal of Computational Elec-
tronics, 2, pp.323-327, 2003.
[52] S. Datta, "The non-equilibrium Green's function (NEGF) formalism: An elemen-
tary introduction," in IEEE International Electron Devices Meeting (IEDM), Dec.
2002, pp. 703-706.
[53] A. Martinez, M. Bescond, J. R. Barker, A. Svizhenko, M. P. Anantram, C. Millar,
and A. Asenov, "A Self-Consistent Full 3-D Real-Space NEGF Simulator for Study-
ing Nonperturbative Effects in Nano-MOSFETs," IEEE Transactions on Electron
Devices, vol. 54, no. 9, pp. 2213-2222, Sept. 2007.
[54] M. P. Anantram, M. S. Lundstrom, and D. E. Nikonov, "Modeling of Nanoscale
Devices," Proceedings of the IEEE, vol. 96, no. 9, pp. 1511-1550, Sept. 2008.
[55] H. Jiang, S. Shao, W. Cai, P. Zhang, "Boundary treatments in non-equilibrium
Greens function (NEGF) methods for quantum transport in nano-MOSFETs,"
Journal of Computational Physics, vol. 227, no. 13, pp. 6553-6573, June 2008.
[56] A. Martinez, A. R Brown, N. Seoane and A. Asenov, "Perturbative vs Non-
Perturbative impurity scattering in a narrow Si Nanowire GAA transistor: A NEGF
study," Journal of Physics, vol. 193, no. 1, 2009, 012047.
[57] A. R Brown, A. Martinez, N. Seoane and A. Asenov, "Comparison of Density Gradi-
ent and NEGF for 3D Simulation of a Nanowire MOSFET," in Spanish Conference
on Electron Devices, Feb. 2009, pp. 140-143.
[58] A. R. Brown, A. Martinez, M. Bescond and A. Asenov, "Nanowire MOSFET vari-
ability: a 3D density gradient versus NEGF approach," in Silicon Nanoelectronics
Workshop, June 2007, pp. 127-128.
[59] A. R. Brown, J. R. Watling, G. Roy, C. Riddet, C. L. Alexander, U. Kovac, A.
Martinez, A. Asenov, "Use of density gradient quantum corrections in the simula-
tion of statistical variability in MOSFETs," Journal of Computational Electronics,
vol. 9, no. 3-4, Dec. 2010, pp. 187-196.
[60] S. Reggiani, E. Gnani, A. Gnudi, M. Rudan, and G. Baccarani, "Low-Field Elec-
tron Mobility Model for Ultrathin-Body SOI and Double-Gate MOSFETs With
Extremely Small Silicon Thicknesses," IEEE Transactions on Electron Devices, vol.
54, no. 9, pp. 2204-2212, Sept. 2007.
[61] D. B. M. Klaassen, "A Unied Mobility Model for Device SimulationI. Model Equa-
tions and Concentration Dependence," Solid-State Electronics, vol. 35, no. 7, pp.
953959, July 1992.
[62] C. Canali, G. Majni, R. Minder, and G. Ottaviani, "Electron and Hole Drift Ve-
locity Measurements in Silicon and Their Empirical Relation to Electric Field and
Temperature," IEEE Transactions on Electron Devices, vol. ED-22, no. 11, pp.
10451047, 1975.
[63] Y. Li, H. -M. Chou, and J. -W. Lee, "Investigation of Electrical Characteristics on
Surrounding-Gate and Omega-Shaped-Gate Nanowire FinFETs," IEEE Transac-
tions on Nanotechnology, vol. 4, no. 5, pp. 510516, Sept. 2005.
[64] J. Yang, J. He, F. Liu, L. Zhang, F. Liu, X. Zhang, and M. Chan, "A Compact
Model of Silicon-Based Nanowire MOSFETs for Circuit Simulation and Design,"
IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 2898-2906, Nov. 2008.
[65] L. Zhang, L. Li, J. He, and M. Chan, "Modeling Short-Channel Effect of Elliptical
Gate-All-Around MOSFET by Effective Radius," IEEE Electron Device Letters,
vol. 32, no. 9, pp. 1188-1190, Aug. 2011.
[66] K. -F. Lee, Y. Li, and C. -H. Hwang, "Asymmetric gate capacitance and dynamic
characteristic
uctuations in 16 nm bulk MOSFETs due to random distribution of
discrete dopants," Semicond. Sci. Technol., vol. 25, no. 4, pp. 045006(8 pages), Apr.
2010.
[67] K. Takeuchi, A. Nishida, and T. Hiramoto, "Random Fluctuations in Scaled MOS
Devices," in SISPAD, pp. 1-7, 2009.
[68] Q. Chen, B. Agrawal, and J.D. Meindl, "A Comprehensive Analytical Subthreshold
Swing (S) Model for Double-Gate MOSFETs," IEEE Transactions on Electron
Devices, vol. 49, no. 6, pp. 1086-1090, June 2002.
[69] Y.-Y. Chen, "DC Characteristic Fluctuation of 16-nm-Gate HKMG Bulk FinFET
Devices Induced by Random Position of Discrete Dopant and Random Grain of
Metal Gate," Master Dissertation, National Chiao Tung University, 2009.
[70] T.K. Chiang, "A new compact subthreshold behavior model for dual-material sur-
rounding gate (DMSG) MOSFETs," Solid-State Electronics, vol. 53, no. 5, pp.
490-496, May 2009.
[71] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate
silicon-on-insulator transistor with volume inversion: A new device with greatly
enhanced performance," IEEE Electron Device Letters, vol. 8, no. 9, pp. 410-412,
Sept. 1987.
[72] H. Nam and C. Shin, "Study of High-k/Metal-Gate Work-Function Variation Using
Rayleigh Distribution," IEEE Electron Device Letters, vol. 34, no. 4, pp. 532-534,
April 2013.
[73] H. Nam and C. Shin, "Comparative study in work-function variation: Rayleigh vs.
Gaussian distribution for grain size," IEICE Electronics Express, vol. 10, no. 9, pp.
1-5, May 2013.
[74] T. Yu, R. Wang, R. Huang, J. Chen, J. Zhuge, and Y. Wang, "Investigation of
Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs,"
IEEE Transactions on Electron Devices, vol. 57, no. 11, pp. 2864-2871, Oct. 2010.
[75] H.-T. Chang, and Y. Li, "Random Dopant Fluctuation in 10-nm-Gate Multi-
Channel Gate-All-Around Nanowire Field Effect Transistors," in Proc. NSTI Nan-
otechnology Conference Expo - Nanotech 2014, vol. 3, pp. 5-8, 2014.