臺灣博碩士論文加值系統

堆疊式電容為動態隨機存取記憶體(DRAM)的關鍵組件。為增加電容值，目前製程大多利用高選擇比之氫氟酸將氮化鈦(TiN)下電極周圍之介電質做濕式等向性回蝕刻(Crown Wet Etching Back Process)，以期達到雙倍表面積的覆蓋率(Surface Area Coverage)之目的。回蝕刻製程後易產生許多副產物與雜質並會重新附著於晶圓表面，進一步影響到製程良率。研究中藉由應用材料公司(Applied Material)所發展之缺陷量測機台做掃描式電子顯微鏡(SEM)外觀分析及X光能量分散光譜(EDS)元素分析後得知副產物成分以碳(Carbon)、矽(Silicon)、鈦(Titanium)及氧(Oxygen)為主。本研究主要目的為找出一個適合高深寬比電容結構的清洗方式，期能去除電容製程後所產生之副產物並避免電容結構倒塌且維持電容間的電子特性。研究方向包含選取適當機台(單片處理機台或批次噴灑式處理機台)及不同種類pH值之混合酸液(EKC6800、REZI38、EKC265、ELM C30、EcoPeeler)。決定出最適當的機台與酸液後，將進一步探討處理時間與旋轉速度對雜質及副產物去除能力之影響。

研究結果顯示之最佳條件為兼具製程容忍度大且雜質去除率最高的條件：酸液EKC265搭配批次噴灑式處理機台。含氰胺(HDA)之化學混合溶劑EKC265，使雜質與基板之間的界面電位(zeta potential)處於同極性而互相排斥，進而提升雜質去除率。氰胺為強氧化還原劑，使金屬氧化物質還原成可溶於異丙酮(IPA)之螯合物。此外選擇應用於EKC265處理時間則不宜過久，若處理時間太長Titanium將被過度回蝕刻，結構易倒塌；然則太短雜質去除率有限，多種不同處理時間經搭配並選擇適當之旋轉速度後所得最佳化條件，可使雜質去除率達到80%。旋轉速度低於650rpm 以下則雜質去除率呈線性，但於650rpm以上去除率則下降；主要原因為化學反應效果於650rpm以上被限制全由物理力量主導所致。

最後的最佳化條件經重複驗證後，被證實可用於60nm以下之動態隨機存取記憶體世代且對於產品良率具有顯著改善。

In a modern stacked-capacitor DRAM device, the structure of the storage capacitor can be thought of as a vertical cylinder made of titanium nitride (TiN). To maximize the capacitance of the cell in high-performance DRAM devices, the dielectric material surrounding the storage nodes needs to be removed during the fabrication process to increase the surface area. This process is known as the crown capacitor wet etch process. However, the wafer surface is highly contaminated by particle defects during the dielectric material removal process. Using Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDS), these particulate defects are shown to be mostly silicon-rich, titanium-rich, carbon-rich and oxygen rich. Particulate defects that appeared on top of the capacitor are the major yield killers for the DRAM device. This study will focus on choosing a suitable tool (between the batch type spray tool and the single wafer tool); and chemical (EKC6800, REZI38, EKC265, ELMC30 and EcoPeeler) with a high residue and particles removal ability. The best optimized cleaning recipe, which includes process time and rotation speed, is developed to provide a sufficient process window for this process.

Also, the results of this work are discussed and analyzed. The batch type process spray tool in combination with the hydroxylamine (HDA) based chemical: EKC265 with high pH, is proved to be efficient in removing particles and residues of high aspect ratio capacitor structures in this work. Zeta potential in the alkaline solution (EKC265) is negative, thus it tends to repel the particles on specimen surface which is also negative-charged. In addition, the combination of HDA and an organic amine form a strong reducing complex solution which can reduced insoluble metal oxide into a lower oxidation state and subsequently chelated with the ligand to form a more soluble metal complex.

Particle count reduces proportionally with chemical treatment time. However, there is a risk of pattern collapse with a long treatment time due to the increment of titanium etch amount. Rotation speed also plays an important rule for particle removal. A higher rotation speed implies stronger external momentum to detach particles. But, it will also limit the efficiency of the chemical reaction. Thus, a balance between chemical reaction and physical reaction has to be considered.
The final optimal condition proves to be significant to yield improvement and is demonstrated to be robust and able to be implemented for 60nm generation DRAM.

Outlines
Chapter 1: Introduction ......1
1.1 DRAM Capacitor ......1
1.2 Wet Cleaning Process......3
1.3 Objectives......6
1.4 Organization of The Thesis and Methods......7
References ......9

Chapter 2: Overview of Particulate Contamination and Adhesion: Defect Sources Analysis ......11
2.1 Introduction ......11
2.2 Origins of Defect and Particles Occurrence.....14
2.3 Types and Composition Analysis of Particles....17
2.3.1 Defect Types Categorization ......18
2.3.2 Analysis of Composition ......19
2.4 Effects of Particulate Contaminations of DRAM Devices ......22
2.4.1 Defect Impact on Wafer Yield Failure...22
2.4.2 Summary of Yield Loss for Each Defect Categorization ...25
2.5 Particle Adhesion in Liquid Bath .......27
2.5.1 Zeta Potential......27
2.5.2 Electric Double Layer Repulsion...... 29
2.5.3 Van der Waals Attraction......30
2.5.4 DLVO Theory......31
2.6 Conclusions......34
References ......35

Chapter 3: Process Parameters and Analysis Methods......37
3.1 Processing Steps & Tools......37
3.1.1 Processing Tool: Single Wafer Type Tool......38
3.1.2 Processing Tool: Batch Type Spray Process Tool......40
3.1.3 Processing Steps......43
3.2 Sample Preparation......43
3.2.1 Crown Capacitor Wet Etch Process......46
3.3 Single Wafer Type Tool......51
3.3.1 Chemical Selection ......51
3.3.1.1 EKC6800......52
3.3.1.2 REZI-38 .....54
3.4 Batch Type Process Tool......54
3.4.1 Chemical Selection......54
3.4.1.1 EKC265......54
3.4.1.2 ELM C30 ......54
3.4.1.3 EcoPeeler......55
3.5 Process Variables Investigated......57
3.6 Detection and Analysis of Particle Defects......57
References......59

Chapter 4: Impact of Process Variables On Wafer Surface Cleaning......61
4.1 Introduction of Experimental Design......61
4.1.1 Chemistries Dependency On Crown Capacitor Particle Defects......62
4.1.1.1 Experimental Result......64
4.1.2 Chemical Process Time Dependency On Crown Capacitor Particle Defects......67
4.1.2.1 Experimental Result...... 68
4.1.3 Chemical Rotation Speed Dependency On Crown Capacitor Particle Defects ......75
4.1.3.1 Experimental Result...... 75
4.2 Discussion......78
4.2.1 Chemical Reaction......78
4.2.1.1 EKC6800 ......78
4.2.1.2 REZI-38 ......80
4.2.1.3 EKC265 ......82
4.2.1.4 ELM C30 ......84
4.2.1.5 EcoPeeler ......85
4.2.1.6 Summary for Chemical Reactions......86
4.2.2 Physical Reaction......88
4.3 Summary and Condition Setup......92
4.4 Repeatability Test and Yield Improvement Result .....93
References......97

Chapter 5 Conclusions and Future Development ......99
5.1 Conclusion ......99
5.2 Future Development......101
References......104

Chapter 1:
1. Lutzen, J., et al., "Integration of capacitor for sub-100-nm DRAM trench technology", VLSI Technology, Digest of Technical Papers, Symposium on 2002, pp. 178-179.
2. Koyanagi, M., "The Stacked Capacitor DRAM Cell and Three-Dimensional Memory", Solid-State Circuits Newsletter, IEEE, 2008. 13(1): pp. 37-41.
3. Takemae, Y., et al., "A 1Mb DRAM with 3-dimensional stacked capacitor cells", Solid-State Circuits Conference, Digest of Technical Papers, IEEE International, 1985, pp. 250-251.
4. Kimura, K., et al., "A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier", Solid-State Circuits, IEEE , 1987, pp. 651-656.
5. Ema, T., et al., "3-dimensional stacked capacitor cell for 16 M and 64 M DRAMS", International Electron Devices Meeting, 1988, Technical Digest., 1988, pp. 592-595.
6. Changhyun, C., et al. "A 6F2 DRAM technology in 60nm era for gigabit densities",VLSI Technology, Digest of Technical Papers, Symposium on. 2005, pp.36-37.
7. Jun Sugiura, "Influence of Contaminants on Device Characteristics", Ultraclean Surface Processing of Silicon Wafers, Springer, Ed. 1998, Japan.
8. Hitsohi, M., Ohmi, T.(Ed), "Principles of Semiconductor Device Wet Cleaning", Scientific Wet Process Technology for Innovative LSI/FPD Manufacturing, Ed. 2006, United States.
9. W. Kern and D.A. Puotinen, "Cleaning solution based on hydrogen peroxide for use in silicon semiconductor technology", 1970, RCA Rev. 31 : pp.187-206.
10. Hattori, D.T., "Ultraclean Surface Processing of Silicon Wafers.", Ultraclean Techonology for VLSI Manucfacturing: An Overview, Springer, Ed. 1995, Japan.
11. Hiroshi, M., Akinobu, T., Hitoshi M., Senri, O., Kenichi M., Ohmi, T.(Ed), "High-Performance Wet Cleaning Technology", Scientific Wet Process Technology for Innovative LSI/FPD Manufacturing, Ed. 2006, United States.

Chapter 2:

1. Hiroshi M., Akinobu T., Hitoshi M., Senri O., Kenichi M., “High-Performance Wet Cleaning Technology”, Scientific Wet Process Technology for Innovative LSI/FPD Manufacturing, Ed. 2006, USA.
2. T. Hattori, Sony, "Contamination Control: Problems and Prospects", Solid State Technology , vol.33, no.7, pp. S1-S8, 1990.
3. Jun Sugiura, "Influence of Contaminants on Device Characteristics", Ultraclean Surface Processing of Silicon Wafers, Springer, Ed. 1998, Japan.
4. K.Werner, “Handbook of semiconductor wafer cleaning technology: science, technology, and applications”, Noyes Publications, Ed. 1993, USA.
5. Ranade, M.B., “Adhesion and removal of fine particles on surfaces”, Aerosol Science & Technology, volume 9, pp.179-191, 1987.
6. Franssila, S., “Introduction to microfabrication”, J.Wiley, Ed. 2004, USA.
7. M. Itano, F.W. Kern, Jr., I. Kawanabe, M. Miyashita, R.W. Rosenberg, and T. Ohmi, “ Particle removal from silicon wafer surface in wet cleaning process”, IEEE transactions on Semiconductor Manufacturing, Volume 6, issue 3, pp.258-267, 1993.
8. M. Itano, T. Kezuka, “Particle adhesion and removal on wafer surfaces in RCA cleaning”, Ultraclean Surface Processing of Silicon Wafers, Springer, Ed. 1998, Japan.
9. D.S. Rimai, L.P. Demejo and R.C. Bowen, “Mechanics of particle adhesion”, Fundamentals of Adhesion and Interfaces, pp.1-23, 2004.
10. B.V. Derjaguin and L.D Landau, “Theory of the stability of strongly charged hydrophobic sols and of the adhesion of strongly charged particles in solutions of electrolytes”, Acta Physicochim USSR, Volume:14, pp. 633, 1941.
11. E.J.W. Verwey and J.T.G. Overbeek, “Theory of the Stability of Hydrophobic Colloids.”, Amsterdam, Elsevier, pp. 118, 1948.
12. C. Ruggiero, M. Mantelli, A.Curtis, S.Zhang, P. Rolfe, “A computer model of the adhesion behaviour of particles under the influence of DLVO and hydrophobic interactions”, Proceedings of the 20th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, vol 6, pp.2838-2841, 1998.

Chapter 3:
1. Nahomi Aoto, NEC, "Goals for Next-Generation Wafer Cleaning Technology, From the Viewpoint of Wafer Surface Conditioning", Ultraclean Surface Processing of Silicon Wafer, Springer, Ed. 1998, Japan.
2. Jae Yong Park, Han-Mil Kim etc. , "Single-wafer process for improved metal contact hole cleaning", Solid State Technology, volume 134, pp.177-180, 2007.
3. Jun Sugiura, "Influence of Contaminants on Device Characteristics", Ultraclean Surface Processing of Silicon Wafers, Springer, Ed(1998), Japan.
4. Jeffery W.Butterbaugh, FSI international, “Wafer Cleaning Techniques For Meeting the Challenges of Advanced Semiconductor Manufacturing”, Semiconductor Manufacturing Magazine, Vol.7, Issue 5, pp. 33-36 May 2006.
5. EKC6800 product sheet, EKC Technology, Inc., Hayward, CA94545, November 2006, http://www2.dupont.com (6 November 2006).
6. Rezi-38 product sheet, Mallinckrodt Baker, Inc., Phillipsburg, NJ 08865, November 2006, http://www.mallbaker.com (11 November 2006).
7. Tatarian, S., SARA 313 Toxic Release Inventory, in III, IHS, Editor. 2009: U.S. Environmental Protection Agency (EPA) - United States.
8. EKC265 product sheet, EKC Technology, Inc., Hayward, CA94545, November 2006, http://www2.dupont.com (6 November 2006).
9. ELM C30 B11 product sheet, Mitsubishi Gas Chemical Company, Inc, Chiyoda-ku, Tokyo 100, Japan, http://www.mgc.co.jp (13 April 2007).
10. EcoPeeler Y101 product sheet, Fine Polymers Corporation, Chiba Prefecture 270-0216, Japan, http://finepolymers.com/ecopeeler-concept (29 Feb 2008).
11. Hattori, T., "Detection and Analysis of Particles in Production Lines", Ultraclean Surface Processing of Silicon Wafers ,Springer, Ed. (1998), Japan.

Chapter 4:
1. Ohmi, T., “Proposal of advanced wet cleaning of silicon surface”. Extended Abstracts of 188th Electrochemical Society Meeting, Chicago, No. 429, pp. 680-681, 1995.
2. Stefan Lutter, “Optimization of a Single Wafer Post-Etch Residue Removal Process” Diplomarbeit, Fachbereich Mikrosystemtechnik, Fachhochschule Regensburg, January, 2000.
3. EKC6800 product sheet, EKC Technology, Inc., Hayward, CA94545, November 2006, http://www2.dupont.com (6 November 2006).
4. Rezi-38 product sheet, Mallinckrodt Baker, Inc., Phillipsburg, NJ 08865, November 2006, http://www.mallbaker.com (11 November 2006).
5. EKC265 product sheet, EKC Technology, Inc., Hayward, CA94545, November 2006, http://www2.dupont.com (6 November 2006).
6. ELM C30 B11 product sheet, Mitsubishi Gas Chemical Company, Inc, Chiyoda-ku, Tokyo 100, Japan, http://www.mgc.co.jp (13 April 2007).
7. EcoPeeler Y101 product sheet, Fine Polymers Corporation, Chiba Prefecture 270-0216, Japan, http://finepolymers.com/ecopeeler-concept (29 Feb 2008).
8. Lee, Wai Mun , “A Proven Sub-Micron Photoresist Stripper Solution For Post Metal and Via Hole Processes”, International Conference on Micro- and Nanofabrication, Volumes 41-42, pp. 377-381, 1998.
9. M. Pourbaix, "Atlas of Electrochemical Equilibria in Aqueous Solutions", Pergamon, 1966, New York.
10. Busnaina, A.A. & Hong Lin, “The Physical Removal of Nanoscale Particles from Surfaces”, Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and workshop, pp.272-277, 1998.
11. Busnaina, A.A. and Gale, G.W, “Removal of Silica Particles from Silicon Substrates Using Megasonic Cleaning,” Journal of Particulate Science and Technology, Vol.15, pp.197-211, 1999.
12. G.M. Burdick, “Describing Hydrodynamic Particle Removal From Surfaces Using the Particle Reynolds Number,” Journal of Nanoparticle Research, volume 3, pp. 455-467, 2001.
13. Tsai, C.J., Pui, D.Y.H. and Liu, B.Y.H., “Particle Detachment from Disc Surfaces of Computer Disk Drives.” Journal of Aerosol Science Technology, volume 15, pp.60-68, 1991.
14. Soltani, M. and Ahmadi,G., “On Particle Adhesion and Removal Mechanisms in Turbulent Flows” Journal of Adhesion Science Technology, volume 8, no. 7, pp. 763-785, 1994.

Chapter 5:
1. Hitsohi, M., Ohmi, T.(Ed), "Principles of Semiconductor Device Wet Cleaning", Scientific Wet Process Technology for Innovative LSI/FPD Manufacturing, Ed. 2006, Japan.
2. Hiroshi M., Akinobu T., Hitoshi M. Senri O., Kenichi, M. , “High-Performance Wet Cleaning Technology”, Scientific Wet Process Technology for Innovative LSI/FPD Manufacturing, Ed. 2006, Japan.
3. P. Kücher, "Lessons Learned from 300mm Conversion for Next Generation Manufacturing," Proceedings of European IEEE/Semi Semiconductor Manufacturing Conference, April 2000, Munich, Semi Technical Publications, Mtn. View, CA.
4. M. Heyns, et al., "Advanced Wet and Dry Cleaning Coming Together for Next Generation," Solid State Technology, pp. 37-47, March 1999.