臺灣博碩士論文加值系統

高速電路中，時脈訊號的傳送是需要高穩定性的，由於電路中有相當多的緩衝級，這將導致時脈的寬度受到不可預期的影響。而時脈訊號的變動可能會使電路效能下降。在傳統脈波寬度鎖定電路之鎖定時間都比較長，這將影響到數位系統之運作。因而，本論文提出一快速脈波週期偵測及脈波產生之脈寬鎖定迴路，以單一條延遲線同時進行脈波調整與脈波偵測機制，藉由硬體共用的方式，減少硬體面積。在相同延遲細胞解析度下，採用128級D型正反器進行脈寬偵測，將時脈訊號轉換為128位元之溫度計碼。接著我們採用溫度計轉二進制電路(Thermometer-to-Binary Circuit)快速轉換溫計碼為七位元的脈波數位碼，相較於傳統使用移位暫存器計數週期的方式可大幅縮短鎖定時間，並在校正電路部分，使用半週期轉換器，於一次的迴路操作即可將脈波寬度鎖定至50%。由於電路操作於高頻時，受限於迴路內部電路延遲時間，因此，我們也提出一高速多對一CMOS多工器，以8組16級傳輸閘與7組2-1 CMOS多工器搭配組合，比起傳統2-1 多工器組成的多對一多工器，不但面積小，並且因為傳輸的級數變少，使電路的延遲時間變得更小，同時整體脈波鎖定迴路的功率及速度都可得到提升。本脈寬鎖定迴路在 0.18um CMOS 1.8V 製程下模擬，並以佈局驗證，操作頻率範圍為100MHz~400MHz，在400MHz下功率消秏為14mW，最大誤差在3%以內，並且於6個時脈週期時間即可鎖定在50%工作週期。

In high speed circuit, clock signal has to be highly stable. However, the many buffer stages in the circuit may impose unexpected effect on clock duty cycle (pulsewidth), which in term lower the circuit performance. Traditional pulsewidth locked circuit requires longer lock time, which may affect the functioning of digital system. This thesis proposed a pulsewidth locked circuit that can quickly detect pulse cycle and produce pulses. The pulsewidth locked circuit used a delay line to adjust and detect pulse simultaneously. Through the hardware-sharing mechanism, the proposed circuit successfully reduced its hardware area. Under the same delay-cell resolution, the circuit adapted a 128-bit pulsewidth detector in 128-bit thermometer code. Then we used thermometer-to-binary circuit to quickly transformed the thermometer code to 7-bit pulse code, which, when compared with traditional application of using shift register to count cycle number, can greatly reduce lock time.

As for the correction circuit we applied a half-cycle converter, which can lock pulsewidth to 50% in one circuit operation. Since the circuit was limited by internal circuit delay when operated with high frequency, we proposed a high-speed, many-to-one CMOS multiplexer to solve this problem. The proposed multiplexer was composed of 8 pairs of level 16 transmission gates and 7 pairs of 2-1 CMOS multiplexers. When compared to traditional many-to-one multiplexer, the proposed multiplexer was not only with smaller area, its circuit delay time was also smaller due to the reduced multiplexer levels, thus enhance the overall speed and performance of the pulsewidth lock loops. The pulsewidth lock circuit was simulated by 0.18um CMOS process under VDD 1.8V. With layout verification, the operating frequency range was between 100 MHz~400 MHz. When the operating frequency was 400 MHz, the power consumption of the proposed pulsewidth lock loops was 14mW, the maximum pulsewidth error was within 3%, and 50% duty cycle can be locked within only 6 clock cycles.

中文摘要 i
英文摘要 ii
目錄 iv
表目錄 vii
圖目錄 viii
一、緒論 1
1.1 研究動機 1
1.2 研究方法 2
1.3 論文架構 2
二、傳統脈波寬度鎖定迴路介紹 4
2.1 數位類比混合式脈波寬度控制電路 4
2.2 全數位式脈波寬度控制電路介紹 6
2.2.1 可調整工作週期之全數位脈波寬度控制電路 6
2.2.2 使用OR-AND之工作週期矯正電路 8
2.2.3 全數位式半工作週期矯正電路 9
2.2.4 全數位工作週期矯正電路 10
2.2.5 全數位快速鎖定迴路之非50%之時脈輸入 11
2.2.6 全數位設計之脈波寬度鎖定迴路 13
2.3 綜合分析討論 14
2.3.1 數位類比混合與全數位比較 14
2.3.2 全數位式設計分析 15
三、新式脈波週期偵測及脈波產生器設計 16
3.1 傳統鎖定迴路之雙延遲線架構 16
3.1.1 延遲細胞解析度分析 17
3.1.2 延遲線與操作頻率範圍之關係 19
3.2 新式單延遲線快速脈波週期偵測及脈波產生器 21
3.2.1 單延遲線架構分析 22
3.2.2 脈波週期偵測器原理 23
3.2.3 脈波產生器原理 24
3.3 多級延遲線設計考量 27
3.3.1 多級延遲細胞元設計 27
3.3.2 延遲線級數考量 29
3.4 實際電路操作頻率範圍 29
四、高速多對一CMOS多工器設計 31
4.1 傳統2-1多工器分析 31
4.2 2-1 多工器組成之多對一多工器型態 33
4.3 高速多對一CMOS多工器設計 36
4.4 多對一多工器效能比較 46
五、快速脈波週期偵測及脈波產生之脈寬鎖定迴路硬體實現與模擬結果 48
5.1 迴路架構與動作流程 48
5.2 內部控制電路介紹 52
5.2.1 溫度計碼轉二進制碼電路與週期偵測電路 52
5.2.2 半週期轉換器與七位元減法器 55
5.2.3 時序控制單元 57
5.2.4 頻率變動偵測機制 58
5.3 硬體實現 59
5.4 模擬結果 70
六、結論 75
參考文獻 76

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