臺灣博碩士論文加值系統

在近代半導體元件與製程的研究與發展中,橫向雙擴散金屬氧化物半導體（Lateral Double-Diffused Metal-Oxide-Semiconductor, LDMOS）由於易於與低電壓的積體電路集成，以形成具有高壓功能的積體電路（High Voltage Integrated Circuits, HVIC）和智能電源管理積體電路（Smart Power Management Integrated Circuits, SPMIC），故已逐漸引起廣泛的探討與研究。
但是,卻少有研究與文獻同時探討製程與元件模擬.因此,本論文將利用製程模擬(SProcess)與元件模擬(SDevice)來設計與探討一個高壓(120 V)的LDMOS元件.
本論文主要是探討與研究BCD（Bipolar-CMOS-DMOS）製程中的LDMOS，而其結構與參數則是建構於矽絕緣體上(Silicon On-insulator, SOI)。而此SOI-LDMOS，是建構在0.8 µm SOI-BCD的製程平台上，其工作電壓為12 V (Vgs)至120 V (Vds)的高電壓元件，而其具備的中等溝槽局部氧化層結構(Medium Trenched Isolation Local Oxidation of Silicon , MTI-LOCOS)被應用於此製程中，以降低寄生效應。
經由Synopsys公司的Sentaurus模擬工具的研究，我們建立了一個系統性的架構來模擬SOI-NLDMOS的製程與結構，並對此元件的電性做深入的探討與研究。這些電性包括臨界電壓，飽和電流，擊穿電壓和自熱(Self-heating)特性等。
SOI-LDMOS雖然具有耐高壓、低漏電流，高運算速度和抗輻射等優點，然而，由於SOI-LDMOS掩埋氧化層的導熱性較差，導致元件的自熱效應。而此自熱效應將造成漏極電流的退化。
在本文中，我們亦將在使用不同的載子傳輸模型(carrier transport models )下,對SOI-LDMOS的自熱效應進行探討。此研究的結果顯示，元件使用不同的載子傳輸模型，對元件模擬的電熱特性與精準度有相當大的差異。根據研究結果，我們在元件結構上做一些改進，以提高元件的熱效率和崩潰電壓，並對此進行探討。

Interest in lateral diffused metal-oxide semiconductors (LDMOSs) has been growing, due to their ease of integration with low voltage circuitry to form high voltage integrated circuits (HVICs) and smart power management integrated circuits (SPMICs). Despite considerable researches, few are found to have explored and documented the process and device simulation at the same time. This study adopted the process simulator SProcess and the device simulator SDevice to design a high-voltage (>120 V) LDMOS.
We investigated an LDMOS structure fabricated using the Bipolar-CMOS-DMOS (BCD) process based on silicon on-insulator (SOI) substrates. This research outlines the development of SOI-LDMOS based on 0.8 µm BCD technology with operating voltage from 12 V (Vgs) to 120 V (Vds). We also proposed a novel medium trenched isolation local oxidation of silicon (MTI-LOCOS) process to reduce the parasitic effect.
Through research using Synopsys Sentaurus simulation tools, we developed a system to simulate the processes involved in device fabrication of SOI-NLDMOS devices. We aim is to understand the effects of process parameters on SOI-LDMOS device characteristics by establishing a simulation methodology calibrated by experimental data. These characteristics included threshold voltage, saturation current, breakdown voltage and self-heating characteristics.
SOI-LDMOS devices have strong ability in sustaining high drain voltage with low power leakage, high operation speed and anti-radiation features. However, SOI-LDMOS transistors suffer from self-heating effect due to poor thermal conductivity of the buried oxide. This effect can cause the degradation of drain current at certain device bias condition.
In this thesis, the self-heating effects within SOI MOSFETs were explored using different carrier transport models. The results of this investigation reveal considerable variations in electrical characteristics and temperature within the device during operation. Based on the results mentioned above, we modified some structures to improve the thermal efficiency and breakdown of the device were explored.

Chinese Abstract ….……….……………….….…….…….……………… i
English Abstract ……….…….……….……….….…………………...…. iii
Acknowledgements …………….……...…….……………….………...… v
Table of Contents ………………………....………………………...…… vi
List of Figures …………………………....….………...………………… ix
Symbols ………………………………………...…...…………...……... xiv
Abbreviations ……………………………...………………….………… xv
Key constants ……………….….……………………………………… xvii
Ⅰ. Chapter 1: Executive Summary …….…….……………………….…… 1
1.1. Brief Introduction …………………………………………….…… 1
1.2. Motivation and Background ….…………………….……......….… 7
1.3. Outline of chapters ….………………………………………......… 9
Ⅱ. Chapter 2: Introduction.…....………………………….…………...…. 10
2.1. Development of Power Devices ………………….................….... 10
2.2. Comparison of Power MOS Devices: Bulk Silicon and SOI ……. 18
2.2.1. What is SOI? ...……..………….………………………….… 19
2.2.2. Manufacturing of SOI wafers.……...………….........……...... 19
2.2.3. Why SOI? .…………………….………….…………………. 21
2.3. TCAD …………….………………………....................……….... 23
2.3.1. Sentaurs TCAD Tools …………...……………….…….…… 23
- vii -
2.3.2. Development of BCD devices …………...………...……… 25
Ⅲ. Chapter 3: Background and Device Operating Principles ……...…... 29
3.1. Device Structure …………………………………………………. 29
3.2. LDMOS Breakdown Mechanism ……......…………....……….… 32
3.2.1. Avalanche breakdown …...………………......……......…... 32
3.2.2. Surface breakdown …...……………………...……....……… 42
3.2.3. Snapback breakdown …...……………………….……...…… 44
3.2.4. Gate oxide breakdown …………...………..............….…...… 46
3.3. Improving Breakdown Characteristics …………………...….… 46
3.3.1. Reduced Surface Field (RESURF) ……................……...…... 46
3.3.2. RESURF in SOI …...………………….….....……......…...… 56
3.4. On-Resistance …...………………………………..………..…..… 62
3.5. Self-heating Effect ...…………….…….………….……………… 66
Ⅳ. Chapter 4: Process Flow and Process Simulation …............….….…. 73
4.1. BCD Process Flow ...……………………..........................……… 73
4.2. Process Simulation …………………………...…………….……. 80
4.2.1. LDMOS Layout and Structure ...….…………............….…... 82
4.2.2. MTI Formatted and N-Well/P-Well Implant ………….......… 84
4.2.3. LOCOS Design and Active Area (AA) .…....….……..…..…. 88
4.2.4. Gate Oxide and Polysilicon Design ………………..…...…… 92
4.2.5. HV-WELL(SPD/SND) Implant …………………......….… 94
4.2.6. Source/Drain Implant …..…………......…….....…......……... 96
- viii -
4.2.7. Contact and Metallization …......…….……..………...…...… 96
Ⅴ. Chapter 5: Comparison and Analysis of SOI-NLDMOS Device: Simulations and Measurement ……………………...… 98
5.1. Analysis of SOI-LDMOS Input Characteristics for IdVgs ……... 101
5.2. Analysis of SOI-NLDMOS Output Characteristics for IdVds … 106
5.3. Improving Self-Heating Conditions.…………...................……. 121
5.4. SOI-LDMOS Device Breakdown ……………………....……… 127
Ⅵ. Chapter 6: Conclusions and Future Work ………….......….…….… 136
6.1. Conclusions …….…………………………………...…….….… 136
6.2. Future Work ………………....…………….…...……………… 137
Bibliography. ………………………………………...............………… 138
Autobiography. ………………………………………………………… 148

[1] 金光明, “高壓Double RESURF LDMOS器件設計與工藝模擬,” 碩士論文, 南通大學, (2008).
[2] I. Y. Park, Y. K. Choi, K.Y. Ko, C. J. Yoon, B. K. Jun, M. Y. Kim, H. C. Lim, N. J. Kim, and K. D. Yoo, “BD180-a new 0.18 µm BCD (Bipolar-CMOS-DMOS) Technology from 7V to 60V,” Proceedings of the 20th International Symposium on Power Semiconductor Devices and IC's,” pp. 64-67, Orlando FL, USA (2008).
[3] A. Parpia, and C. A. T. Salama, “Optimization of RESURF LDMOS Transistors: An Analytical Approach,” IEEE Transaction on Electron Devices. 37.3, pp. 789-796, (1990).
[4] C. Contiero, A. Andreini, and P. Galbiati, “Roadmap Differentiation and Emerging Trends in BCD Technology,” Proceeding of the 32nd European Solid-State Device Research Conference, pp. 275-282, Firenze, Italy (2002).
[5] K. Kawamoto, and S. Takahashi, “An Advanced No-Snapback LDMOSFET with Optimized Breakdown Characteristics of Drain n-n+ Diodes,” IEEE Transaction on Electron Devices, 51.9, pp. 1432-1440 (2004).
[6] P. Wessels, M. Swanenberg, H. van Zwol, B. Krabbenborg, H. Boezen, M. Berkhout, and A. Grakist, “Advanced BCD technology for automotive, audio and power applications,” Solid-State Electronics, 51.2, pp. 195-211, Elsevier, Amsterdam, Netherlands (2007).
[7] R. Rudolf, C. Wagner, L. O'Riain, K. H. Gebhardt, B. Kuhn-Heinrich, B. von Ehrenwall, A. von Ehrenwall, M. Strasser, M. Stecher, U. Glaser, S. Aresu, P. Kuepper, and A. Mayerhofer, “Automotive 130nm Smart-Power-Technology including embedded Flash Functionality,” Proceedings of the 23rd International Symposium on Power Semiconductor Devices and ICs, pp. 20-23, San Diego, California, USA (2011).
[8] H. Tomita, H. Eguchi, S. Kijima, N. Honda, T. Yamada, H. Yamawaki, H. Aoki, and K. Hamada, “Wide-Voltage SOI-BiCDMOS Technology for High-Temperature Automotive Applications,” Proceedings of the 23rd International Symposium on Power Semiconductor Devices and ICs, pp. 28-31, San Diego, California, USA (2011).
[9] Y. Hao, P. C. Sim, B. Toner; M. Frank, M. Ackermann, A. Tan, U. Kuniss, E. Kho, J. Doblaski, E. G. Hee, M. Liew, A. Hoelke, S. Wada, and T. Oshima, “A 0.18μm SOI BCD technology for automotive application,” Proceedings of the 27th International Symposium on Power Semiconductor Devices and IC's, pp. 177-180, Hong Kong, China (2015).
[10] 陳志勇, 黃其煜, 龔大衛, “BCD工藝概述,” 半導體技術, 第31卷第9期, pp. 641-644, 河北省石家莊市, 中國 (2006).
[11] I. Y. Park, Y. K. Choi, K. Y. Ko, S. C. Shim, B. K. Jun, N. C. Moon, N. J. Kim, K. D. Yoo, “BCD (Bipolar-CMOS-DMOS) Technology Trends for Power Management IC,” Proceedings of the 8th International Conference on Power Electronics and ECCE Asia, pp. 318-325, Jeju South, Korea (2011).
[12] B. Murari, F. Bertotti, G A. Vignola, Smart Power ICs: Technologies and Applications, 2nd edition, Springer Science & Business Media, New York, USA (2002).
[13] B. J. Baliga, Modern Power Devices, Wiley, New York, USA (1987).
[14] P. Moens and G. Van Den Bosch, “Characterization of Total Safe Operating Area of Lateral DMOS Transistors,” IEEE Transactions on Device and Materials Reliability, 6.3, pp.349-357 (2006).
[15] Synopsys Inc., “Sentaurus TCAD, Industry-Standard Process and Device Simulators,” Mountain View, California, USA (2012).
[16] H. Ballan, “High-Voltage CMOS and Scaling Trends,” Proceedings of the Electrochemical Society, 2003, pp. 6, Pennington, New Jersey, USA (2003).
[17] B. J. Baliga, “Trends in Power Semiconductor Devices,” IEEE Transaction on Electron Devices, 43.10, pp. 1717-1731 (1996).
[18] H. Zitta, “Smart Power Integrated Circuits,” UNSECO-encyclopedia of life support system (EOLSS) (2013).
[19] A. Emadi, Advanced Electric Drive Vehicles, Chemical Rubber Company (CRC), Boca Raton, Florida, USA (2014).
[20] M. T Thompson, “Notes 01 Introduction to Power Electronics,” Thompson Consulting, Inc. Marion, USA (2005).
[21] B. Kumar, and S. B. Jain, Electronic Devices and Circuits, PHI Learning Pvt. Ltd., Delhi, India (2014).

[22] J. H. Krenz, Electronic Concepts-An Introduction, Cambridge University Press., Cambridge, England (2000).
[23] R. G. Hoft, Semiconductor Power Electronics, Springer Science & Business Media., New York, USA (2012).
[24] Euzeli dos Santos, and E. R. da Silva, Advanced Power Electronics Converters: PWM Converters Processing AC Voltages, Wiley, New York, USA (2015).
[25] Kharagpur, Power Semiconductor Devices, Module 1, Version 2 EE IIT (Indian Institute of Technology Kanpur), Kharagpur, India (2012).
[26] M. Cirstea, A. Dinu, M. McCormick, and J. G. Khor, Neural and Fuzzy Logic Control of Drives and Power Systems, Newnes, Oxford, United Kingdom (2002).
[27] H. Wang, “Power MOSFETs with Enhanced Electrical Characteristics,” Ph. D. Dissertation, University of Toronto, (2009).
[28] B. J. Baliga, “An Overview of Smart Power Technology,” IEEE Transaction on Electron Devices, 38.7, pp. 1568-1575 (1991).
[29] F. E. Holmes, and C.A.T. Salama, “VMOS-A New MOS Technology,” Solid-State Electron, 17.8, pp. 791-797, Elsevier, Amsterdam, Netherlands (1974).
[30] V. A. K. Temple, and P. V. Gray, “Theoretical Comparison of DMOS and VMOS Structures for Voltage and On-resistance,” Proceedings of the International Electron Devices Meeting, 25, pp. 88-92, Washington DC, USA (1979).
[31] D. Ueda, H. Takagi, and G. Kano, “A New Vertical Power MOSFET Structure with Extremely Reduced On-resistance,” IEEE Transactions on Electron Devices, 32.1, pp. 2-6 (1985).
[32] S. C. Sun, and J. D. Plummer, “Modeling the On-resistance of LDMOS, VDMOS and VMOS Power Transistor,” IEEE Transaction on Electron Devices, 27.2, pp. 356-367 (1980).
[33] 陸鑫, “利用TCAD軟件優化兼容於BCD工藝的LDMOS結構,” 碩士論文, 上海交通大學微電子學院, (2010).
[34] P. M. Holland, and P. M. Igic. “An alternative process architecture for CMOS based high side RESURF LDMOS transistors,” Proceedings of the 25th International Conference on Microelectronics, pp. 195-198, University of Nis, Serbia (2006).
[35] U. Radhakrishna, A. DasGupta, N. DasGupta, and A. Chakravorty, “Modeling of SOI-LD MOS Transistor Including Impact Ionization, Snapback, and Self-Heating,” IEEE Transactions on Electron Devices, 58.11, pp. 4035-4041 (2011).
[36] T. Lekshmi, A. K. Mittal, A. DasGupta, A. Chakravorty, and N. DasGupta, “Compact Modeling of SOI-LDMOS Including Quasi-Saturation Effect,” Proceedings of the 2nd International Workshop on. Electron Devices and Semiconductor Technology, pp. 1-4, Mumbai, India (2009).
[37] M. J. Swanenberg, and W. J. Kloosterman, “Modeling of High Voltage SOI-LDMOS Transistor including self-heating,” In Simulation of Semiconductor Processes and Devices. pp. 246-249, Springer Vienna, New York, USA (2001).
[38] M. Tachimori, “SIMOX Waters (Silicon waters with a thin superficial silicon film separated.” Nippon steel technical report, No. 73 (1997).
[39] S. Bengtsson. “Wafer bonding and smartcut for formation of silicon-on-insulator materials,” Proceedings of the 5th International Conference on Solid-State and Integrated Circuit Technology, pp. 745-748, Beijing, China (1998)
[40] H. Mendez, “Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications,” SOI Industry Consortium, (2009).
[41] H. Yamaguchi, H. Himi, H. Fujino and T. Hattori, “Intelligent power IC with partial SOI structure,” Japanese Journal of Applied Physics, 34, pp. 864, Tokyo, Japan (1995).
[42] J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI , 3rd edition Springer Science & Business Media, Boston, USA (2004).
[43] F. Udrea, “SOI-based devices and technologies for High Voltage ICs,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp. 74-81, Boston, USA (2007).
[44] Synopsys. Inc., “Sentaurus Device User Guide, Version D-2010.03,” Mountain View, California, USA (2010).
[45] A. U. Kashif, "Optimization of LDMOS Transistor in Power Amplifiers for Communication Systems," Ph. D. Dissertation, Linköpings Universitet, Sweden, (2010).
[46] H. Matthew. “Semiconductor TCAD Fabrication Development for BCD Technology”. Ph. D. Dissertation, Worcester Polytechnic Institute, (2006).
[47] Synopsys Inc., “Sentaurus device simulator (release D-2010.03),” Mountain View, California, USA (2010).
[48] J. A. Appels and H. M. J. Vaes, "High-Voltage Thin Layer Devices (RESURF DEVICES)," Proceedings of the International Electron Devices Meeting, 25, pp. 238-241, Washington D.C , USA (1979).
[49] M. F. Chang, G. Pifer, H. Yilmaz, E. J. Wildi, R. G. Hodgins, K. Owyang, and M. S. Adler, "Lateral HVIC with 1200-V Bipolar and Field-Effect Devices," IEEE Transactions on Electron Devices, 33.12, pp. 1992-2001 (1986).
[50] A. W. Ludikhuize, “A review of RESURF technology,” Proceedings of Power Semiconductor Devices and ICs, Proceedings of the 12th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp.11-18, Toulouse, France (2000).
[51] J. L. Sanchez, M. Gharbi, H. Tranduc, and P. Rossel, “Quasi-saturation Effect in High Voltage VDMOS Transistors," IEE Proceedings I-Solid-State and Electron Devices, 132.1, pp. 42-46 (1985).
[52] M. N. Darwish, “Study of the Quasi-Saturation Effect in VDMOS Transistors,” IEEE Transactions on Electron Devices, 33.11, pp. 1710-1716 (1986).
[53] A. A. Orouji, and M. Mehrad, “The Best Control of Parasitic BJT Effect in SOI-LDMOS With SiGe Window Under Channel,” IEEE Transactions on Electron Devices, 59.2, pp. 419-425 (2012).
[54] U, Radhakrishna, “Compact Modeling of SOI-LDMOS Transistor including Impact Ionization, Snapback and Self Heating,” Ph. D. Dissertation, Indian Institute of Technology Madras, (2001).
[55] 潘俊廷, “SOI 功率元件分析,” 碩士論文, 逢甲大學, (2002).
[56] J. M. Park, “Novel Power Devices for Smart Power Applications,” Ph. D. Dissertation, University of Vienna, (2004).
[57] A. Resfa, B. R. Menezla, and M. Benchhima, “Simulating and modeling the breakdown voltage in a semi-insulating GaAs P+N junction diode,” Journal of Semiconductors, 35.8: 084002, Beijing, China, (2014).
[58] V. Anantharam, and K.N Bhat. “Analytical Solutions for the Breakdown Voltages of Punched-Through Diodes Having Curved Junction Boundaries at the Edges,” IEEE Transaction on Electron Devices, 27.5, pp. 939-945 (1980).
[59] B. J. Baliga, Fundamentals of Power Semiconductor Devices, 2nd edition, Springer Science & Business Media, New York, USA (2010)
[60] B. J. Baliga, Modern Power Devices, 1st edition, Wiley, New York, USA (1987).
[61] A. S. Grove, O. Leistiko, and W. W. Hooper, “Effect of surface fields on the breakdown voltage of planar silicon p-n junctions,” IEEE Transaction on Electron Devices, 14.3, pp. 157-162 (1967).
[62] H. A. Schafft, “Second Breakdown–A Comprehensive Review,” Proceedings of the IEEE, 55.8, pp.1272-1288 (1967).
[63] B. El-Kareh, and R. J. Bombard, Introduction to VLSI Silicon devices, Physics Technology and characterization, 2nd edition, Kluwer Academics publishers, Boston, USA (1986).
[64] H. Ballan, and M. Declerq, High voltage devices and circuits in standard CMOS technologies, Springer Science & Business Media, Boston, USA (1999).
[65] J. A. Appels, and H. M. J. Vaes, “HV Thin Layer Devices (RESURF Devices),” Proceedings of the International Electron Devices Meeting, 25, pp. 238-241, Washington DC, USA (1979).
[66] H. J. Sigg, G. D. Vendelin, T. P. Cauge, and J. Kocsis, “D-MOS transistor for microwave applications,” IEEE Transactions on Electron Devices, 19.1, pp. 45-53 (1972).
[67] A. Asif, “Laterally Diffused Metal Oxide Semiconductor Transistor on Ultra-thin Single-crystalline Silicon,” Ph. D. Dissertation, University of Stuttgart, (2011).
[68] K. Sung, and T. Won. “High-side N-channel LDMOS for a High Breakdown Voltage,” Journal of the Korean Physical Society, 58.5, pp. 1411-1416 (2011).
[69] G. S. May, and S. M. Sze, Fundamentals of Semiconductor Fabrication, Wiley, New Jersey, USA ( 2003).

[70] P. M. Holland, T. K. H. Starke; S. Hussain; W. M. Jamal, P. A. Mawby, and P. M. Igic. “Novel 2-D RESURF LDMOSFET in 0.6µm CMOS Technology for Power ICs,” Proceedings of the 24th International Conference on Microelectronics, 1, pp. 133-136, NiS, Serbia (2004).
[71] J. A. Appels, M. Collet, P. Hart, H. Vaes, and J. Verhoeven, “Thin layer high voltage devices (RESURF DEVICES),” 35.1, pp. 1-13, Philips Journal of Research (1980).
[72] M. Amato, and V. Rumennik, “Comparison of lateral and vertical DMOS specific on-resistance,” Proceedings of the International Electron Devices Meeting, 31, pp. 736-739, Washington DC, USA (1985).
[73] T. Efland, S. Malhi, W. Bailey, O.K. Kwon, and W.T. Ng, “An Optimized RESURF LDMOS Power Device Module Compatible with Advanced Logic Processes,” Proceedings of the International Electron Devices Meeting, pp.237-240, San Francisco CA, USA (1992).
[74] Y. S. Huang, and B. J. Baliga, “Extension of RESURF principle to directly isolated power device,” Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, pp. 27-30, Baltimore Maryland, USA (1991).
[75] 富力文, 閻力大, “RESURF原理應用於SOI LDMOS晶體管,” 半導體學報, 17.4, pp. 283-288, 北京, 中國 (1996).
[76] A. Popescu, F. Udrea, and W. Milne, “A numerical study of the RESURF effect in bulk and SO1 power devices,” Proceedings of the International Semiconductor Conference, 1, pp. 127-130, Sinaia, Romania (1997).
[77] J. He, X. Xi, M. Chan, C. Hu, Y. Li, Z. Xing, and R. Huang, "Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances," Semiconductor science and technology, 17.7, pp. 721, Bristol, United Kingdom (2002).
[78] G. Shan, C. Junning, K. Daoming, and F. Miao,“Analysis of Self-heating Effect and Breakdown Characteristics in Partial SOI LDMOS with Multi Silicon Windows,” Proceedings of the 7th International Conference on ASIC, pp. 1237,-1240, Guilin, China (2007).
[79] E. Arnold, “Silicon-on-Insulator Devices for High Voltage and Power IC Applications,” Journal of The Electrochemical Society, 141.7, pp. 1983-1988 (1994).
[80] X. Luo, X. Wang, G. Hu, Y. Fan, K. Zhou, Y. Luo, Y. Fan, Z. Zhang, Y. Mei, and B. Zhang. "Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch," Journal of Semiconductors, 35.2: 024007, Beijing, China (2014).
[81] 孟堅, 高珊, 陳軍寧, 柯導明, 孫偉鋒, 時龍興, 徐超.“用阱作高阻漂移區的LDMOS 導通電阻的解析模型,”半導體學報, 26.10, pp. 1983-1988, 北京, 中國 (2005).
[82] P. Dey, A. Rafique, S. Adhikari, S. Ghosal, S. Biswas, S. Das, K. Choudhary, A. Biswas, A. K. Bandyopadhyay, and S. Mandal. "AN SOI LDMOS FOR BETTER SWITCH APPLICATION INCREASING THE DRIFT REGION OF AN N-MOS: A COMPARATIVE STUDY," Journal of Electron Devices, 14, pp. 1142-1150, Beirut, Lebanon (2012).
[83] Y. K. Leung, A. K. Paul, K. E. Goodson, J. D. Plummer, and S. S. Wong, “Heating Mechanisms of LDMOS and LIGBT in Ultrathin SOI,” IEEE Electron Device Letters, 18.9, pp. 414-416 (1997).
[84] Q. Qian, W. Sun, J. Zhu, and L. Shi, “Investigation of the shift of hotspot in lateral diffused LDMOS under ESD conditions,” Microelectronics reliability, 50.12, pp. 1935-1941. Elsevier, Amsterdam, Netherlands (2010).
[85] M. J. Swanenberg and W. J. Kloosterman, “Modelling of High-Voltage SOI-LDMOS Transistors including Self-Heating,” Simulation of Semiconductor Processes and Devices, Springer Vienna, New York, USA (2001).
[86] Z. Lun, G. Du, J. Qin, Y. Wang, J. Wang, and X. Liu, “Investigation of Self-heating Effect in SOI-LDMOS by Device Simulation,” Proceedings of the 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-3, Xi’an, China (2012).
[87] J. Roig, D. Flores, S. Hidalgo, M. Vellvehi, J. Rebollo, and J. Millian, “Study of novel techniques for reducing self-heating effects in SOI power LDMOS,” Solid-State Electronics, 46.12, pp 2123-2133, Elsevier, Amsterdam, Netherlands (2002).
[88] P. L. Hower, "Safe Operating Area: A New Frontier in LDMOS Design,” Proceedings of the 14th International Symposium on Power Semiconductor Devices and ICs, pp. 1 (2002).
[89] Synopsys Inc., “Sentaurus Technology Template: LDMOS Processing,” Mountain View, California, USA (2007).
[90] M. S. Sulong, A. A. Jamry, S. M. S. Shuib, R. Sanudin, M. Morsin, and M. Z. Sahdan,“Process and Device Simulation of 80nm CMOS Inverter Using Sentaurus Synopsys TCAD,” Proceedings of the FEIIC Symposium on Engineering and Technology, pp. 427-432, Kuching, Sarawak, Malaysia (2008).
[91] V. Parthasarathy, R. Zhu, V. Khemka, T. Roggenbauer, A. Bose, P. Hui, P. Rodriquez, J. Nivison, D. Collins, Z. Wu, I. Puchades, and M. Butner, "A 0.25μm CMOS based 70V smart power technology with deep trench for high-voltage isolation,” Proceedings of the International Electron Devices Meeting, pp. 459-462, San Francisco, CA, USA (2002).
[92] N. H. Kim, H. Y. Yoo and E. G. Changa, "Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory,” Solid State Phenomena, 124, pp. 29-32, Trans Tech Publications, Pfaffikon, Switzerland (2007).
[93] X. Cao, D. Nicholson, W.A. Nevin, and J. Knopke. “Control of Crystalline Defects in Trench Isolated Thick Film SOI for High Voltage Smart Power ICs,” Crystalline Defects and Contamination: Their Impact and Control in Device Manufacturing III : DECON 2001 : Proceedings of the Satellite Symposium to ESSDERC 2001, Nuremberg, Germany, 2001, pp. 103, Electrochemical Society, Erlangen, Germany (2001).
[94] A. Raman, D. G. Walker, and T. S. Fisher, “Simulation of nonequilibrium thermal effects in power LDMOS transistors,” Solid-State Electronics, 47.8, pp. 1265-1273, Elsevier, Amsterdam, Netherlands (2003).
[95] A Aminbeidokhti, A. A. Orouji, S. Rahmaninezhad, and M. Ghasemian, “A Novel High-Breakdown-Voltage SOI MESFET by Modified Charge Distribution,” IEEE Transactions on Electron Devices, 59.5, pp. 1255-1262 (2012).
[96] A. C. T. Aarts, and W. J. Kloosterman, “Compact Modeling of High-Voltage LDMOS Devices Including Quasi-Saturation,” IEEE Transactions on Electron Devices, pp. 53.4, pp. 897 (2006).
[97] N. Prasad, P. Sarangapani, K. N. S. Nikhil, N DasGupta, A. DasGupta and A. Chakravorty, “An Improved Quasi-Saturation and Charge Model for SOI-LDMOS Transistors,” IEEE Transactions on Electron Devices, 62.3, pp. 919-926 (2015).
[98] W. Lie, and S. Yang “Analysis and modeling of quasi-saturation effect in high-voltage LDMOS transistors,” Acta Physica Sinica, 59.1, pp. 571-578, Beijing, China (2010).
[99] O. Triebl, “Reliability Issues in High-Voltage Semiconductor Devices,” Ph. D. Dissertation, University of Vienna, (2012).
[100] K Pradeep, “Exploring the Nano-Scale Self-Heating Mechanisms in SOI/Bulk MOS Devices,” Ph. D. Dissertation, École Polytechnique Fédérale de Lausanne, (2015).
[101] E. Pop, S. Sinha, and K.E. Goodson, “Heat Generation and Transport in Nanometer-Scale Transistors,” Proceedings of the IEEE, 94.8, pp. 1587-1601 (2006).
[102] Y. G. Chen, S. Y. Ma, J. B. Kuo, Z. Yu, and R. W. Duton, “An Analytical Drain Current Model Considering Both Electron and Lattice Temperatures Simultaneously for Deep Submicron Ultrathin SO1 NMOS Devices with Self-Heating,” IEEE Transactions on Electron Devices, 42.5, pp. 899-906 (1995).
[103] C. Anghel, A. M. Ionescu, N. Hefyene, and R. Gillon, "Self-Heating Characterization and Extraction Method for Thermal Resistance and Capacitance in High Voltage MOSFETs," Proceedings of the 33rd European Solid-State Device Research Conference (ESSDERC), pp. 449-452, Estoril, Portugal (2003).
[104] W. Jin, , W. Liu, S. K. Fung, P. C. Chan, and C. Hu, "SOI Thermal Impedance Extraction Methodology and Its Significance for Circuit Simulation," IEEE Transactions on Electron Devices, 48.4, pp. 730-736 (2001).
[105] I. Cortes, P. Fernandez-Martinez, D. Flores, S. Hidalgo, and J. Rebollo, "Punch-through Effects in RF Bulk LDMOS Transistors," Proceedings of the Spanish Conference on Electron Devices (SCED), pp. 344-347, Madrid, Spain (2007).
[106] G. Shahidi, A. Ajmera, F. Assaderaghi, R. Bolam, A. Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, H.-S. Lo, M. Maloney, D. Moy, W. Rausch, D. Sadana, D. Schepis, M. Sherony, J.W. Sleight, L. F. Wagner, K. Wu, B. Davari, and T. C. Chen, “Mainstreaming of the SOI technology,” Proceedings of the IEEE International SOI Conference, pp. 1-4, Rohnert Park, California, USA (1999).