[1] P.Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits”,IEEE Trans. on Comput, 1981.
[2] C.F. Wu, C.T. Huang, K.L. Cheng, and C.W. Wu, “Simulation-Based Test Algorithm Generation for Random Access Memories”, IEEE, 2000.
[3] A.J. van de Goor, “Using March Tests to Test SRAMs”, IEEE, 1993.
[4] C.F. Wu, C.T. Huang, and C.W. Wu, “RAMSES:a fast memory fault simulator”, on Proc. Int. Symp. Defect and Fault Torlerance in VLSI System, 1999.
[5] K.Chakrabarty and B.T.Murray, “Design of built-in test generator circuits using width comperssion,” IEEE Trans. Computer-Aided Design,1988.
[6] IEEE Std 1149.4, ”IEEE Standard for a Mixed-Signal Test Bus”,1999.
[7] “IEEE standard for VHDL Register Transfer Level (RTL) synthesis”, IEEE-SA Standards Board, 1999.
[8] M.A. Breuer, A.D. Friedman, “Diagnosis & Reliable Design of Digital System”, 1976.
[9] H.Y. Chang E. Manning and G. Metze, “Fault Diagnosis of Digital System”, 1970.
[10] KEF-Tech, “WINDRIVER V4 Developer’s Guide”, KRF-Tech, 2000.
[11] 何昌祐,”DSP應用於PC-Based運動控制器之技術分析”,機械月刊第二十四卷第二期。[12] 林傳生, “使用VHDL電路設計語言之數位電路設計”, 儒林圖書有限公司, 1998.
[13] 唐佩忠, “VHDL與數位邏輯設計”, 高立圖書有限公司, 1999.
[14] 陳周造, “Borland C++ Builder by 100 Example入門與應用”, 博碩文化股份有限公司, 1997.