臺灣博碩士論文加值系統

電子產品越來越進步，隨著功能越來越多元，一個產品內部可能整合了多種的訊號，而訊號彼此會引響干擾，因而使得整體效能的降低，這就是所謂的EMI(Electromagnetic Interference)，而這些電磁波也會對人體產生一定的傷害，所以現在的電子產品都必須要能通過安規才能量產上市，由於以上的原因，展頻電路(Spread Spectrum Clock Generator)因此被需要而發展了起來。
鎖相迴路被廣泛的使用在訊號產生器上面，所以大部分的展頻電路會以鎖相迴路來作為基礎來進行電路的設計，固本論文將以鎖相迴路設計一個展頻電路，本文第一個晶片是以開迴路的設計來規劃整個電路，首先完成一個鎖相迴路達到所需要工作頻率的區段，確定迴路穩定之後，再壓控震盪器的其中一極進行額外的控制，而本論文是改以三角波進行控制，使其整個迴路所產生的頻率有展頻的效果，而此方式的好處是晶片面積小，功率消耗小就可以達到展頻的效果，但是也因為開迴路的設計，所以展頻量是不能很精準的控制，還有下線之後的製程變異可能也會使得實際的展頻量變的較無法與預估之展頻量一樣。
有鑒於開迴路設計的展頻電路會無法控制展頻量，所以又規劃了一個使用閉迴路系統的展頻電路，主體架構為兩個延遲鎖相迴路(DLL)和一個鎖相迴路(PLL)，參考訊號同時輸入給兩個延遲鎖相迴路藉由兩個延遲鎖相迴路產生參考訊號的十分之九和十分之十一倍的訊號，再傳出給後面的多工器(MUX)，經由多工器來選擇鎖相迴路參考訊號的來源看是要十分之九還是十分之十一倍的訊號，藉由多工器切換參考訊號來源達到展頻的目的，同時也可以從切換次數的多寡來控制展頻量，因為是閉迴路的設計所以展頻量變成是自己控制的，同時也不會被製程變異所影響。

With the progress of the electronic technologies ,most of the EMI from the system is caused by clock drivers and synchronized circuit .In order to reduce the EMI from the system clocks ,spread spectrum clock techniques that modulate the system clock frequency have been proposed.
PLL has been widely used in the clock generator ,so this paper designs spread spectrum clock generator on PLL circuit .In first chip ,I design a PLL based on open loop ,this chip can spread spectrum by one stage in VCO circuit that injection the triangle wave .It can be modulate by triangle wave .This chip has advantage of low power consume and small area . Open loop design and progress variation also made shortcoming that can not precise control of spread spectrum .
Second chip is a closed loop circuit . The following is the architecture of two DLL and one PLL circuit . Input the reference clock to DLL circuit and than it can produce two signal , 9/10 times and 11/10 times reference clock . Select that two reference clock to PLL by mux .
And this chip can spread spectrum and control spread spectrum value by the mux switch . Because it was closed loop so it can precise control of spread spectrum .
In this thesis , we make two chip for spread spectrum clock generator , and the chip simulation and measurement successfully .

摘要 I
ABSTRACT II
目錄 III
表錄 V
圖錄 VI
第一章 - 1 -
1.1動機與目的 - 1 -
1.2論文概要 - 2 -
第二章 - 3 -
2.1 鎖相迴路操作原理與組成元件介紹 - 3 -
2.1.1 相頻偵測器(PFD) - 4 -
2.1.2 充電泵(CP) - 9 -
2.1.3 迴路濾波器(LF) - 10 -
2.1.4壓控振盪器(VCO) - 11 -
2.1.5 除頻器(FD) - 14 -
2.2 迴路分析 - 15 -
2.2.1推導公式 - 15 -
2.3 SSCG 展頻方法介紹 - 20 -
第三章 - 23 -
3.1開迴路展頻時脈產生器設計概念 - 23 -
3.2 MATLAB 整體迴路轉移函數運算 - 24 -
3.3電路架構 - 26 -
3.3.1 相頻偵測器(PFD) - 27 -
3.3.2 充電泵(CP) - 29 -
3.3.3 壓控振盪器(VCO) - 32 -
3.4 總迴路模擬 - 35 -
3.5 晶片量測 - 37 -
第四章 - 43 -
4.1閉迴路展頻時脈產生器設計概念 - 43 -
4.2電路架構 - 44 -
4.3延遲鎖相迴路(DLL) - 45 -
4.3.1 Start-up電路 - 46 -
4.3.2 相頻偵測器(PFD) - 47 -
4.3.3 充電泵(CP) - 49 -
4.3.4壓控延遲鏈(VCDL) - 52 -
4.3.5 Dummy電路 - 55 -
4.3.6 11/10倍頻率相位選擇器(PSC) - 56 -
4.3.7 9/10倍頻率相位選擇器(PSC) - 59 -
4.3.8 Mux電路 - 61 -
4.4鎖相迴路(PLL) - 62 -
4.5總迴路模擬 - 63 -
4.6晶片量測 - 66 -
第五章 - 74 -
結論 - 74 -
FUTURE WORK - 74 -
BIBLIOGRAPHY - 75 -

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