臺灣博碩士論文加值系統

雙極性靜電吸盤(Electrostatic Chuck,ESC)已經在一系列的電漿製程環境中被研發使用，它的優勢是在於它不需加入電漿即可以有吸附能力，所以在業界逐漸廣泛運用。而雙極性ESC之上下電極比例、電極材料、表面粗糙度、表面紋路、結合膠的選用、晶圓與雙極性ESC之間的氦氣壓力分佈以及雙極性ESC的背後水冷設計都對雙極性ESC性能優劣有決定性的影響。實驗過程中，我們以鋁金屬作為雙極性ESC的重要材料，並將鋁表面作硬陽極處理來形成第一層介電層，上下電極的面積比例也以互補的靜電吸力作有效的均勻分配，結合膠的選用乃採用熱膨脹係數低、介電常數低、熱傳係數大與結合力強的Epoxy系列結合膠作為第二層介電層。我們利用所建構的高密度電漿環境測試平台，以VB為軟體介面、高感度感測器為硬體介面和RS-232為通訊介面，來測試我們所設計的雙極性ESC之吸附晶片、釋放晶片及晶片散熱的能力。從實驗中發現，在工作電壓未達崩潰電壓情形下，ESC的吸附能力與工作電壓成正比關係。ESC介電層的電阻率降得越低，則ESC吸附與釋放的時間越短，而表面粗糙度越好有助於雙極性ESC的熱傳效率的改善與介電層電阻率的下降。藉由此實驗所得到的數據可以提供設計雙極性ESC上有一個較完善的設計準則，並提供研發廠商一個雙極性ESC的測試平台，對於往後掌握雙極性ESC製程良率有很大的助益。

The bipolar electrostatic chuck for silicon wafers has been developed for used in serial plasma process. The advantage of the bipolar electrostatic chuck is that attractions appear without plasma, so we take advantage of it in industry gradually. The bipolar electrostatic chuck’s proper proportion between the top plate and the bottom plate, material of plates, roughness of plate’s surface, marking of plate’s surface, the choice of the gelatin, the disposal of helium’s pressure between the wafer and the bipolar electrostatic chuck and the rear of the bipolar electrostatic chuck’s cooling water design affect the quality of the bipolar electrostatic chuck importantly.
In the experiment, the aluminum material is used for the bipolar electrostatic chuck , and hard anodizing is applied to aluminum to build the first dielectric layer. The proper proportion between the top plate and the bottom plate of the bipolar electrostatic chuck is effectively uniformly distributed by the reciprocative electrostatic attraction. The low dilation coefficient, the low dielectric coefficient, the high thermal coefficient and the strong binding are the main factors in the choice of the gelatin. The gelatin, which is a kind of Epoxy is used to build the second dielectric layer. We build the high density plasma’s test stage which is built by Visual Basic that is a software interface, high sensitivity sensor that is a hardware interface and RS-232 that is a message interface. The stage tests the bipolar electrostatic chuck’s abilities of suction, delivery and cooling. We can find some key points in the experiment. When the working voltage is less than the breakdown voltage, there is a direct proportion between suction and working voltage. When the resistivity of the bipolar electrostatic chuck’s dielectric layer is lower, the time of suction and the time of dechucking is shorter. Better roughness of surface yields better thermal efficiency and lower resistivity of dielectric layers. From the data of the experiments, we can give the bipolar electrostatic chuck a better design principle, and we can also provide manufacturers a test stage that can be used to produce better quality products.

目 錄
誌謝---------------------------------------Ι
摘要---------------------------------------Ⅱ
英文摘要-----------------------------------Ⅲ
目錄---------------------------------------Ⅴ
圖表目錄-----------------------------------Ⅶ
第一章:簡介與文獻回顧----------------------1
1.1前言--------------------------------1
1.2研究目的----------------------------1
1.3文獻回顧---------------------------2
第二章:理論架構分析------------------------6
2.1靜電吸盤的理論分析----------------------6
2.2電漿環境的理論分析---------------------14
第三章:雙極性靜電吸盤量測系統設計 --------18
3.1雙極性靜電吸盤的製作---------------18
3.2平面式電漿環境的製作---------------25
3.2.1 電漿腔體的製作-------------25
3.2.2 電漿管路的製作----------------------28
3.2.3 RF電漿產生器的配置-----------------32
3.2.4 自動化量測系統的配置-------34
第四章:量測系統操作-----------------------38
4.1雙極性靜電吸盤的操作---------------38
4.2電漿環境的操作---------------------40
第五章實驗量測與數據分析------------------42
5.1雙極性靜電吸盤吸附能力測試 ------------42
5.1.1量測方式以及概念 --------------------42
5.1.2 量測步驟 --------------------------43
5.2雙極性靜電吸盤吸附與釋放時間測試 ------46
5.3雙極性靜電吸盤上晶片溫度分佈測試---47
第六章:結果與討論-------------------------56
第七章:未來展望---------------------------58
參考文獻----------------------------------59

[1] Shone, A.J.,“Gate oxide charging and its elimination for metal antenna capacitor and transistor in VLSI CMOS double layer metal technology,”VLSI Technology Symp, pp. 73 (1989)
[2] Stamper, A.K. and S.L. Pennington,“Passivation-layer charge-induced failure mechanism in 0.5μm CMOS technology,”IEEE VLSI Multilevel interconnection Conference (VMIC), pp. 420 (1992)
[3] Strong, A.W.,“Gate dielectric integrity and reliability in 0.5μm CMOS technology,” IEEE Int. Reliability Physics Symp. (IRPS), pp. 18 (1993)
[4] Stamper, A.K., J.B. Lasky, and J.W. Adkisson,“Plasma- induced gate-oxide charging issues for sub-0.5μm complementary metal-oxide-semiconductor technologies,”J. Vac. Sci. Technol. A, vol. 13, pp. 905 (1995)
[5] Cheung, K.P. and C.S. Pai,“Charging Damage from Plasma Enhanced TEOS deposition,” IEEE Electron Dev., vol. 16, pp. 220 (1995)
[6] Cote, D.R.,“Low temperature chemical vapor deposition processes and dielec- trics for microelectronic circuit manufacturing at IBM. IBM J. Res. Develop,”vol. 39, pp. 437 (1995)
[7] Machida, K.,“Charge build-up reduction during biased electron cyclotron resonance plasma deposition,” J. Vac. Sci. Technol. B, vol. 13, pp. 2004 (1995)
[8] Bothra, S.,“Control of Plasma Damage to Gate Oxide during High density Plasma Chemical Vapor Deposition,”J. Electrochem. Soc, vol. 142, pp. 208 (1995)
[9] Krishnan, S.and S. Nag.,“Assessment of charge-induced damage from high density plasma (HDP) oxide deposition,”International Symposium on Plasma Process Induced Damage, pp. 67 (1996)
[10] Cheung, K.P.,“Plasma Charging Damage,”London: Spinger-Verlag, vol. 346, pp. 35 (2000)
[11] Cheung, K.P.,“Is n-MOSFET hot-carrier lifetime degraded by charging dam-
age International Symp,”Plasma Process Induced Damage (P2ID), pp. 186 (1997)
[12] Cheung, K.P.,“Impact of plasma-charging damage polarity on MOSFET noise,”International Electron Device Meeting (IEDM), pp. 437 (1997)
[13] Krishnan, S.,“Antenna Device Reliability for ULSI Processing,”International Electron Device Meeting (IEDM), pp. 601 (1998)
[14] Cote, D.,“Process-induced gate oxide damage issues in advanced plasma chemical vapor deposition processes,”International Symp Plasma Process Induced Damage (P2ID), pp. 61 (1996)
[15] Cheung, K.P.,“On the mechanism of plasma enhanced dielectric deposition charging damage,”International Symposium on Plasma Process Induced Damage (P2ID), pp. 161 (2000)
[16] Joshi, M., J.P. McVittie, and K. Saraswat,“Direct Experimental Determination and modeling of VUV Induced Bulk Conduction in Dielectrics during Plasma processing,”International Symposium on Plasma Process Induced Damage
(P2ID), pp. 157 (2000)
[17] Watanabe Toshiya, Kitabayashi Tetsuo and Nakayama Chiaki, “Electrostatic force and absorption current of alumina electrostatic chuck,” Jpn.J.Appl.Phys, vol.31, no.7, pp. 2145-2150 (1992)
[18] Larry D.Hartsough,“Electrostatic wafer holding,”Solid State Technology, pp. 887-90 (1993)
[19] 高密度電漿設備之開發與乾蝕刻應用，大葉大學電機工程所 碩士論文， 蘇天佑 民91

[20] 外置式線圈離子化物理氣相沉積系統之電漿特性量測， 清華大學物理研究所 碩士論文，王聖元 民91
[21] 利用感應耦合電漿輔助濺鍍多功能性薄膜，成功大學化工所 碩士論文， 鄭有宏 民90
[23] 感式高密度電漿源之研製與量測分析，清華大學工程與系統科學所 碩士論文，巫尚霖 民87