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The major objective of this research is to develop a
general dispatchingmodel for the photolithography area,
bottleneck area, in the wafer fabricationfactory. This research
first analyzes the manufacturing process and
machinecharacteristics in wafer fabrication to find out the
important factors whichinfluence on the performance the most
in the photolithography area as well asthe entire factory. By
carefully considering these factors, a dispatchingmodel,
PADR, for machines in the photolithography area is developed.
In this research, an AUTOSCHED simulation model for a real world
factory isconstructed and the corresponding statistical
hypotheses testing is designedso that the significance of the
above factors to the system performance can beanalyzed and
finally different dispatching strategies under different mixed
ofsystem properties for the photolithography area can be
derived. The simulationresults indicate that PADR can
effectively balance load, reduce average cycletime and waiting
time, and increase throughput rate. Also, larger
improvementscome from input contorl policy than from
dispatching rule, in particular, FW(Fixed-WIP) provides
improved performance over UL(Uniform-Loading) input.
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