臺灣博碩士論文加值系統

雙邊緣觸發正反器(Dual Edge Triggered Flip Flop)是一種利用正緣與負緣觸發而進行資料存取的電路，由於雙邊緣觸發正反器只需要單邊緣觸發正反器一半的時脈頻率就能達到相同的資料存取，進而減少功率消耗。本論文提出之具優化脈衝產生器之高性能雙邊緣觸發正反器，藉由優化的脈衝產生器改善正向脈衝與負向脈衝之間的延遲可能導致競爭條件(Race Condition)的問題而導致栓鎖功能不正常，同時讓脈衝更有對稱性以及改善整體電路的驅動力，進而設計高性能的雙邊緣觸發正反器，本論文電路模擬使用TSMC 45 奈米製程，以HSPICE軟體模擬於室溫25℃與供應電壓1.0V下之電路行為。實驗結果顯示本論文的設計與相關研究比較正向脈衝與負向脈衝之間的延遲減少48%、脈衝產生器之脈衝平均上升時間最多減少65%、平均下降時間最多減少60%，脈波寬度方面則增加32%。

Dual-edge triggered flip-flop is a kind of storage that can perform the write operation at both positive and negative clock edge. Compared to the traditional single-edge triggered flip-flop, because the dual-edge triggered flip-flop has the same performance at half the clock rate, it is widely used to reduce the clock power consumption. In this thesis, we propose a refined pulse generator to improve the performance of dual-edge triggered flip-flop. By reducing the delay between the positive and negative pulse, our design can eliminate the race condition problem that possibly causes the circuit failed. In addition, our design has the strong driver and the symmetrical feature. We use the TSMC 45nm technology process with 1.0V supply voltage to implement the proposed design. Compared to the related work, the HSPICE simulation results show that our design can reduce the pulse rise time and fall time by 65% and 60%, respectively, and reduce the delay between the positive and negative pulse by 48%, such that the performance of dual-edge triggered flip-flop can be improved effectively.

第一章 簡介 1
第二章 正反器 4
2.1 傳統單邊緣觸發正反器 6
2.2 傳統雙邊緣觸發正反器 8
2.3 雙邊緣觸發正反器之類型 10
第三章 文獻探討 13
3.1 相關研究-雙邊緣觸發正反器 14
3.1.1 單一時脈內嵌式雙邊緣觸發正反器 14
3.1.2 外接式雙邊緣觸發正反器 16
3.2 相關研究-XOR/XNOR產生電路 22
第四章 具優化脈衝產生器之高性能雙邊緣觸發正反器 26
4.1 本論文提出之8T外接式脈衝產生器 28
4.2 本論文使用之6T脈衝觸發栓鎖 34
4.2.1 輸入資料D=High時之栓鎖工作原理 34
4.2.2 輸入資料D=Low時之栓鎖工作原理 35
第五章 模擬結果分析 38
5.1 外接式脈衝雙邊緣觸發正反器之波型比較 39
5.2 工作頻率功能測試 46
5.3 其他數據比較 49
5.3.1 平均上升時間與平均下降時間 50
5.3.2 減少Pulse與PulseB(XOR/XNOR)之間的延遲 52
5.3.3 脈衝寬度比較 52
5.3.4 功率消耗 53
5.3.5 電晶體個數比較 55
第六章 結論與未來展望 57
第七章 參考文獻 58

[1]M. Afghahi,J .Yuan, “Double Edge-Triggered D-Flip Flop For High-Speed CMOS Cirsuits,” IEEE Solid-Stats Circuits, vol. SC-26, no. 8, pp. 1168-1170, Aug. 1991.

[2]Jinn-Shyan Wang “A New True-Single-Phase-Clocked Double-Edge-Triggered Flip Flop for Low-Power VLSI Designs,” IEEE International Symposium on Circuits and Systems, Hong Kong, pp. 1896-1899, June 9-12. 1997.

[3]Kuo-Hsing Cheng,Yung-Hsiang Lin , “A Dual-Phase –Clock Double Edge Triggered Flip Flop for Low Voltage and High Speed Application,”Proceedings of the International Symposium on Circuits and Systems, vol. 5, pp. 425-428, 2003.

[4]Jin-Fa Lin, Ming-Hwa Sheu, Peng-Siang Wang“A Low Power Dual-Mode Pulse Triggered Flip Flop Using Pass Transistor Logic,” IEEE International Symposium on next-Generation Electronics(ISNE), pp. 203-206, Nov. 2010.

[5]Jian-Ping Gong, “Dual-Edge Triggered Flip Flop With High Performance And High Soft-Error Tolerance,” in Proc.Eletronic Circuits and Semiconductor Devices, April. 2011.

[6]Ahmed M.Shams, Tarek K.Darwish, Magdy A.Bayoumi“Performance Analysis Of Low-Power 1-Bit CMOS Full Adder Cells,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 20-29, Feb 2002.

[7]Mariano Aguirre-Hernandez, Monico Linares-Aranda, “CMOS Full-Adders for Energy-Efficient Arithmetic Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 718-721, Apr. 2011.

[8]Majid Amini Valashani , Sattar Mirzakuchaki“A Novel Fast,Low-Power And High-Performance XOR-XNOR Cell,” IEEE International Symposium on-next Generation Eletronics(ISNE),Circuit and Systems(ISCAS), Aug, 2016.

[9]Yi-Wen Wu,.O.T.-C and Ruey-Liang Ma, “A Low-Power Digital Signal Processor Core By Minimizing Inter-Data Switching Activities,” Circuits and Systems,2001,MWSCAS 2001,Proceedings of the 44th IEEE 2001 Midwest Symposium on,Volume: 1,2001 page(s):172-175 vol.1

[10]Neil Weste,David Harris, “Integra Circuit Design,” 4th ed,Pearson,2010

[11]J. Yuan, C. Svensson, “High-speed CMOS circuit technique,” IEEE Journal Solid-Stats Circuits, vol. 24, pp. 62-70, Feb. 1989.

[12]Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka,“A Fully Static Topologically-Compressed 21-Transistor Flip Flop with 75% Power Saving,” IEEE Journal Solid-Stats Circuits, vol. 47, no. 11, pp. 2526-2533, Nov. 2014
.
[13]Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai,“Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Struture Reduction Schemes,”IEEE Transactions on very large scale integration(VLSI) systems, vol. 25,No. 11, page(s):3033-3044, Nov. 2017.

[14]Guang-Ping Xiang, Ji-Zhong Shen, Xue-Xiang Wu. Liang Geng, “Design of a low-power pulse-triggered flip flop with conditional clock technique,” IEEE International Symposium on Circuit and Systems, pp. 121-124, May. 2013.

[15]J.Monteiro,J.Rinderknecht,S.Devadas,“Optimization of Combinational and Sequential Logic Circuit For Low Power Using Precomputation,” Proceedings Sixteenth Conference on Advanced Research in VLSI, pp. 430-444, Mar. 1995.

[16]Ming-Der Shieh,Chin-Long Wey,P.D. Fisher, “A Scan Design For Asynchronous Sequential Logic Circuits Using SR-Latches,” Proceedings of 36th Midwest Symposium on Circuit and Systems, pp. 1300-1303 vol.2, Aug. 1993.

[17]John P. Uyemura, “Introduction to VLSI Circuits and Systems,” 1st ed, Wiley, 2001.

[18]Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuit:A Design Perspective,”2nd ed, Pearson, 2003.

[19]Charles H.Roth,Jr, Larry L.Kinney, “Fundamentals of Logic Design,” 6th ed, 2009.
[20]National Chip Implementation Center, http://www.cic.org.tw.

[21]Wikipedia, https://zh.wikipedia.org/wiki/Wikipedia