臺灣博碩士論文加值系統

隨著摩爾定律的預測發展，3D-IC提供一種提高集成度的方法。其中矽穿孔(Through Silicon Via, TSV)為其中的關鍵組成，因為矽穿孔提供3D-IC封裝新的互連技術。矽穿孔技術的優點包括有:多功能異質整合、功率損耗減少、產品微型化、元件性能提升。本研究利用高頻結構模擬軟體(ANSYS HFSS)對矽穿孔模型進行訊號傳輸模擬，然後擷取矽穿孔模型的S參數(S-parameters)。
本論文研究多個矽穿孔之間的傳輸訊號特性，並探討當更改TSV的結構參數對每個頻段的影響，例如:絕緣層厚度、TSV直徑、高度、間距、RDL寬度、矽基板導電率。觀察更改錐形TSV的角度對傳輸訊號特性的影響，並與圓柱、同軸、不規則之TSV比較。還有模擬當TSV在製程過程中產生空隙會對傳輸訊號特性之影響，藉由ANSYS HFSS模擬TSV結構內如果有空隙的S參數與TSV結構內沒有空隙的S參數進行比對。最後利用五層daisy chain TSV模擬凸塊(Bump)開路或短路對訊號傳遞影響。

3D-IC evolved with the prediction of Moore''s Law, 3D-IC provides a way to improve integration, among which Through Silicon Via (TSV) is a key component, because TSV provides 3D-IC package new interconnect technology. The advantages of TSV technology include: versatile heterogeneous integration, reduced power loss, product miniaturization, and improved component performance. In this thesis , the EM simulation software (ANSYS HFSS) was used to simulate the signal transmission of the TSV model, and then the S-parameters of the TSV model were extracted.
This thesis first studies the transmission signal characteristics between multiple TSVs and discusses the effects of changing the structural parameters of TSV, such as: insulation thickness, TSV diameter, height, pitch, RDL width, silicon substrate conductivity. The changing of the angle of the tapered TSV will affect the transmission signal characteristics, and the results are also compared with the cylindrical, coaxial, and irregular TSV shapes. Second, we study the S-parameter of different position of open or short defects in TSV. Open defects may occur when a bump, connecting two TSVs, is not properly realized because of an inaccurate metal filling. The short defects can be created with the expansion of the bump, RDL, during the stacking process. In second part, the S-parameter of TSV without defect is analysis as a reference; then we analyzed the S-parameter curves of TSV with open/short defects. The analysis of the effects of any position and different quantities of defects can provide a help for a non- invasive defect detection.

摘要 I
ABSTRACT II
誌謝 IV
目錄 V
第一章 緒論 1
1.1 前言 1
1.2研究目的與動機 2
1.3論文架構 3
第二章 矽穿孔(TSV)結構原理的電特性 4
2.1 矽穿孔(TSV)結構的等效電路 4
2.2 在高頻結構模擬軟體(ANSYS HFSS)建構TSV 21
2.2.1 TSV模型結構設計 22
2.2.2 TSV模擬結構利用ANSYS HFSS模擬 23
第三章 TSV結構參數之高頻特性分析 26
3.1 TSV結構參數之高頻特性分析 26
3.1.1 更改絕緣層的厚度的影響 27
3.1.2 更改TSV間距的影響 29
3.1.3 更改TSV直徑的影響 31
3.1.4 更改TSV高度的影響 33
3.1.5 更改RDL寬度的影響 35
3.1.5 更改矽導電率的影響 37
3.2 不同形狀TSV模擬 39
3.2.1 不同角度的錐形TSV 39
3.2.2 不規則形狀TSV 45
3.2.3 同軸TSV 49
第四章 具有缺陷之TSV模擬分析 53
4.1 集膚效應 53
4.2 具有缺陷之TSV模擬分析 55
4.3 TSV凸塊(Bump)的開路跟短路模擬 66
第五章 結果與討論 69
參考文獻 70

[1]http://www.nims.go.jp/mana/research/results/2011/09211/
[2]Kim, Joohee, et al. "High-frequency scalable electrical model and analysis of a through silicon via (TSV)." Components, Packaging and Manufacturing Technology, IEEE Transactions on 1.2 (2011): 181-195.
[3]S. Adamshick, D. Coolbaugh, and M. Liehr, “Experimental characterization of coaxial through silicon vias for 3D integration,” Microelectron. J., vol. 46, no. 5, pp. 377–382, 2015.
[4]H. John, Lau, evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration, Proceeding of International Symposium on Advanced Packaging
[5]M. L. M. Ji, J. Cline, D. Secker, K. Cai, J. Lau, P. Tzeng, C. Zhan, and C. Lee, "3D Si Interposer Design and Electrical Performance Study," in Proc. DesignCon, Santa Clara, CA, USA, Jan. 2013, no. 1-WA2, pp. 1–23.
[6]D. M. Jang, C. Ryu, K. Y. Lee, B. H. Cho, J. Kim, T. S. Oh, W. J. Lee, and J. Yu, Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)," in Proc. Electronic Components and Technology Conference, May 2007, pp. 847~852.
[7]E. M. Chow, V. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C. F. Quate, and T. W. Kenny, Process Compatible Polysilicon-Based Electrical Through-Wafer Interconnects in Silicon Substrates," IEEE/ASME Journal of Microelectromechanical Sysems, vol. 11, no. 6, pp. 631~640, Dec. 2002.
[8]C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC modeling and analysis of Cu, W, and CNT based through-silicon vias (TSVs) in 3-D ICs,” in IEDM Tech. Dig., 2009, pp. 521–524.
[9]M. Celik, A. C. Cangellaris, and A. Yaghmour, “An all-purpose transmission-line model for interconnect simulation in SPICE,” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1857–1867, Oct. 1997.
[10]J. H. Lau, “Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration,” ASME J. Electron. Packag., 136(4), p. 040801-1~ 040801-15, 2014
[11]Ryu S K, Lu K H, Zhang X, et al., “Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects,” IEEE Transactions on Device and Materials Reliability, Vol. 11, No. 1, pp. 35-44, 2011.
[12]Ko C T, Chen K N., “Reliability of key technologies in 3D integration,” Microelectronics Reliability, Vol. 53, No. 1, pp. 7-16, 2011.
[13]Heegon Kim; Jonghyun Cho; Myunghoi Kim; Kiyeong Kim; Junho Lee; Hyungdong Lee; Kunwoo Park; Kwangseong Choi; Hyun-Cheol Bae; Joungho Kim; Jiseong Kim, "Measurement and Analysis of a High-Speed TSV Channel," Components, Packaging and Manufacturing Technology, IEEE Transactions on , vol.2, no.10, pp.1672,1685, Oct. 2012
[14]S. Melamed, F. Imura1, M. Aoyagi, H. Nakagawa1, K. Kikuchi, M. Hagimoto, “Investigation of Effects of Die Thinning on Central TSV Bus Driver Thermal Performance,” 20th International Workshop on Thermal Investigations of ICs and Systems, 24-26 September 2014, Greenwich, London / UK, pp1~5.
[15]Sukumaran V, Bandyopadhyay T, Sundaram V, Tummala R. Low-cost thin glass interposers as a superior alternative to silicon and organic interposers for packaging of 3-d ics. IEEE Trans Compon, Pack Manuf Technol Vol .2, No.9, pp. 1426–33, 2012.
[16]“Signal and power integrity analysis in 2.5D integrated circuits (ICs) with glass, silicon and organic interposer,” 2015 IEEE 65th Electronic Components and Technology Conference (ECTC) , San Diego, CA, 26-29 May 2015, pp. 738 – 743