跳到主要內容

臺灣博碩士論文加值系統

(216.73.216.110) 您好!臺灣時間:2026/05/02 22:57
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:鄭國偉
研究生(外文):Kuo-Wei Cheng
論文名稱:使用0.18umCMOS實現多頻帶之電壓控制環型振盪器
論文名稱(外文):Implementation of a multi-band Voltage-Controlled Ring Oscillator Using 0.18 um CMOS
指導教授:鄭木火
指導教授(外文):Mu-Huo Cheng
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:41
中文關鍵詞:電壓控制振盪器環型振盪器多重路徑
外文關鍵詞:VCOring oscillatormultiple-pass
相關次數:
  • 被引用被引用:0
  • 點閱點閱:434
  • 評分評分:
  • 下載下載:114
  • 收藏至我的研究室書目清單書目收藏:0
本論文提出一個具有多頻帶的電壓控制環型振盪器
(Voltage-Controlled Ring Oscillator)。
一般具有多重路徑 (multiple-pass) 的環型振盪器,
大都是設計在提升振盪器的振盪頻率。
本論文利用多重路徑觀念,
設計出可以使其振盪頻率減慢的連接方式。
然後再利用 NMOS 作為開關電路,
將加快振盪頻率的多重路徑振盪器電路與減慢振盪頻率的多重路徑振盪器電路結合在一起。
由 NMOS
開關的切換去改變電路的連接路徑,如此可得到更大的頻率調整範圍之振盪電路。
由此設計, 每一差動放大級及所需開關共需使用 12 顆 MOS
電晶體, 其中有 8 顆 是 NMOS 及 4 顆是 PMOS。
本論文並以台灣積體電路製造股份有限公司 (TSMC) 0.18
$\mu m$ 1P6M CMOS
製程來模擬一含九級差動放大的電壓控制環型振盪器。 由後端模擬結果
(Post-Sim) 顯示, 在工作電壓為 1.8V 下, 此振盪器的消耗功率為 91.4
mW, 在中心頻率為2GHz, 偏移頻率1MHz情況下, 相位雜訊為 -115.8 dBc/Hz,
振盪頻率範圍可達到 0.32GHz-1.8GHz,
其輸出的峰對峰 (peak-to-peak) 振幅最小值可至 1.67V。
This thesis presents a multi-band voltage-controlled
ring oscillator via the multiple-pass connection,
resulting in a wide range of oscillation
frequency. Most multiple-pass ring oscillators
are designed to increase the oscillation frequency. In
this thesis, we also
exploit the concept of multiple-pass to design a
multiple-pass ring oscillator which can decrease the
oscillation frequency.
A connection is designed via the NMOS
switch to combine together the two circuits all via the
concept of multiple-pass such that a wider range of
oscillation frequency can be obtained.
Hence, we obtain a voltage-controlled oscillator with
two frequency bands which can be easily controlled by
the on/off of the NMOS switches.
We design a nine-stage ring
oscillator; each stage consists of twelve MOS
transistors including eight NMOS transistors and four PMOS
transistors. This oscillator is simulated using 0.18
$\mu m,$ 1P6M CMOS technology provided by
Taiwan Semi-Conductor Manufacturing Company.
The post simulation of the design oscillator, under
the supply voltage of 1.8 V, shows that the required
power is 91.4 mw, the phase noise is -115.8 dBc/Hz at a 1-MHz offset from a 2-GHz center frequency,
the frequency tuning range is from 0.32GHz to 1.8GHz, and
the minimum peak-to-peak output swing is 1.67V.
目錄...........................................i
中文摘要.......................................i
英文摘要.......................................ii
誌謝...........................................iii
圖目錄.........................................vi
表目錄.........................................viii
第一章 緒論....................................1
1.1 電壓控制振盪器重要性及其應用...............1
1.2 文獻回顧與研究動機.........................1
1.3 研究目的...................................2
1.4 論文架構...................................2
第二章 環型振盪器電路原理與架構................3
2.1 環型振盪器基本架構.........................3
2.1.1 單端輸出環型振盪器.......................3
2.1.2 雙端差動輸出環型振盪器...................6
2.2 具多重路徑之環型振盪器架構之探討...........12
第三章 多頻帶環型振盪器電路之設計..............17
3.1 減慢振盪頻率的多重路徑環型振盪器...........17
3.2 以MOS作為開關之分析........................18
3.3 利用NMOS連接後之電路架構與模擬結果.........21
3.4 相位雜訊...................................25
第四章 模擬結果與比較..........................28
4.1 佈局模擬結果與製程變動分析.................28
4.2 線性度.....................................30
第五章 結論....................................39
5.1 結論.......................................39
參考文獻.......................................40
[1]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[2]S.-J. Lee, B. Kim, and K. Lee, ``A Novel High-speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed-delay Scheme," IEEE J. Solid-State Circuits, vol. 32, pp. 289-291, Feb. 1997.
[3]A. Ong, S. Benyamin, J. Cancio, V. Condito, T. Labrie, Q. H. Lee, J. P. Mattia, D. K. Shaeffer, A. Shahani, X. Si, H. Tao, M. Tarsia, W. Wong and M. Xu, ``A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology," IEEE J. Solid-State Circuits} vol. 38, pp. 2155 - 2168, Dec. 2003.
[4]Y. A. Eken and J. P. Uyemura, ``A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18-um CMOS," IEEE J. Solid-State Circuits, vol. 39, pp. 230-233, Jan. 2004.
[5]C. H. Park and B. Kim, ``A Low-Noise, 900-MHz VCO in 0.6-um CMOS," IEEE J. Solid-State Circuits, vol. 34, pp. 586-590, May 1999.
[6]P. R. Gray, Analysis and Design of Analog Integrated Circuits, John Wiley \& Sons, 2001.
[7]L. Dai and R. Harjani, ``Design of Low-Phase-Noise CMOS Ring Oscillators," IEEE Trans. Circuits Syst. II, vol. 49, pp. 328-338, May 2002.
[8]A. Hajimiri, S. Limotyrakis, and T. H. Lee, ``Jitter and Phase Noise in Ring Oscillators," IEEE J. Solid-State Circuits, vol. 34, pp. 790-804, June 1999.
[9]P.V.A. Mohan, V. Ramachandran and M.N.S. Swamy, Switched Capacitor Filters, Prentice Hall ,1995.
[10]H.O. Johansson and C. Svensson, ``Time Resolution of NMOS Sampling Switches Used on Low-Swing Signals," IEEE J. Solid-State Circuit, vol. 33, pp. 237-245, Feb. 1998.
[11]W.S.T. Yan and H.C. Luong, ``A 900-MHz CMOS Low-Phase-Noise Voltage-Controlled Ring Oscillator," IEEE Trans. Circuits Syst. II, vol. 40, pp. 216-221, Feb. 2001.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top