臺灣博碩士論文加值系統

鎖相迴路(PLL)被廣泛地使用於系統晶片(SoC)中。相對於傳統的類比PLL，全數位鎖相迴路(ADPLL)採用數位的設計方法，使其能夠很容易地在先進CMOS製程下與其他的數位電路集合成電路系統。當製程技術或需求規格改變時，重新設計一個PLL時是很耗費時間的。所以為了減少重新設計PLL的時間與努力，使用標準單元(Standard Cell)實現的ADPLLs可以具有最佳的攜帶性，更適合用於SoC設計上。
在ADPLL的所有功能單元之中，數位控制振盪器(DCO)是最重要的組成元件。因為DCO通常佔據了晶片中的最大面積，也是最主要的功率消耗來源。此外，DCO也決定了ADPLL的主要性能，如輸出的頻率範圍、輸出抖動。最重要的是，ADPLL目前已經大量的應用於各種不同的設計需求上，例如: 展頻電路(spread-spectrum clock generator)、快速鎖定(fast settling)頻率合成器。所以，自動化設計流程的ADPLL是必須的，藉以加速整個設計流程。
因為傳統PLL通常鎖定時間都很長，因此導致PLL不常關閉，也因此當系統待命時，一直在運作的PLL的功率消耗就變成SoC待機(Standby)功率消耗的主要來源。若是PLL能快速鎖定頻率及相位，也能讓電路更快地待機，讓PLL早點可以被關閉以減少耗能。
因此，在本論文中，我們設計出透過ADPLL compiler產生及佈局架構彈性、線性的DCO，低耗能、快速鎖定之全數位鎖相迴路來避免掉上述的問題，並以90 奈米製程標準元件庫實現，用以驗證我們所提出的ADPLL compiler設計。

Phase-locked loop (PLLs) are widely used in a system-on-a-chip (SoC). In contrast to analog PLLs, all-digital phase-locked loops (ADPLLs) use digital design approaches which allows it to be easily integrated with other digital circuits into the systems in advanced CMOS process. In order to reduce the design time and design efforts when processes or specifications are changed, ADPLLs which implemented with standard cells have best portability and suitable for the SoC as compared with analog PLLs.
Among the functional blocks of the ADPLL, digitally controlled oscillator (DCO) is the most critical component. Because the DCO usually occupies the most portions of the chip area and consumes relative large power consumption than the other blocks of the ADPLL. Furthermore, DCO dominates the major performance of the ADPLL, such as the output frequency range, and output jitter. According to different design requirements for realizing an ADPLL for various applications, such as a spread-spectrum clock generator (SSCG), a fast settling ADPLL, an automatic design flow for the ADPLL is demanded in order to speed up the overall design process and reduce design turnaround time.
Traditionally, PLL usually takes long lock-in time. Thus for power management of the SoC, PLL can’t be turned off for reducing the standby power consumption. The continuous operating PLLs often dominate the standby power consumption of the system. If the PLL can quickly achieve lock-in and then the PLL can be turned off for reducing energy consumption.
Therefore, an ADPLL which has a fast settling that generated by an ADPLL compiler with liberty timing files is presented in this thesis. The proposed ADPLL has following characteristics: fast lock-in time, low power consumption and a flexible DCO architecture with high linearity. In addition, the test chip is implemented and tapeouted in 90nm CMOS process to verify the proposed ADPLL compiler.

摘要 V
Abstract VI
Content IX
List of Figures XI
List of Tables XIV
Chapter 1 Introduction 1
1.1 Introduction of PLL 1
1.2 Prior PLL/ADPLL Compiler 3
1.2.1 PLL Compiler 3
1.2.2 ADPLL Compiler 6
1.2.3 Interconnect RC Estimation 8
1.3 Conventional Fast Lock-In Methods 10
1.3.1 Flying Adder Based Frequency Synthesizer 10
1.3.2 TDC Based Fast Lock-in Method 12
1.3.3 Without TDC-Based Phase Synthesizer 15
1.3.4 Frequency Estimation Algorithm 17
1.5 Motivation 21
1.6 Thesis Organization 23
Chapter 2 All-Digital Phase-Locked Loop Compiler with Liberty Timing Files 24
2.1 The Proposed ADPLL Compiler Overview 24
2.2 The Proposed DCO Architecture 27
2.2.1 Coarse-Tuning Stage 27
2.2.1 Fine-Tuning Stage 30
2.3 The Proposed Frequency Range Estimation Algorithm 32
2.3.1 Liberty Timing File 32
2.3.2 Non-Linear Delay Model 35
2.3.3 Wire Load Delay 41
2.4 The Proposed Regular Placement Method 45
2.5 Automatic DCO Generation Flow 55
2.6 Frequency Range Estimation Results 57
2.6.1 Pre-Layout Simulation 57
2.6.2 Post-Layout Simulation 60
2.7 Summary 61
Chapter 3 Circuit Design and Implementation of ADPLL 63
3.1 The Proposed Fast Lock-in ADPLL overview 63
3.2 The Proposed Fast Lock-in ADPLL overview 65
3.3 Monotonic DCO Embedded Cyclic TDC 69
3.4 Phase and Frequency Detector 71
3.5 Test Chip Implementation 73
Chapter 4 Full Chip Experimental Results 75
4.1 Specifications 75
4.2 Simulation Results 80
4.2.1 Fast lock-in Simulation 80
4.2.2 Phase Noise and Jitter of Output Clock 83
4.2.3 Chip Summary 86
4.2.4 Comparison Table 88
Chapter 5 DCO Linearity and Monotonicity Discussion 90
5.1 DNL Simulation 90
5.1.1 Coarse-Tuning Stage 90
5.1.2 Fine-Tuning Stage 95
5.2 Frequency Estimation Issue 98
5.2.1 DCO Without Cyclic TDC 98
5.2.2 DCO With 33 Stages Cyclic TDC 100
5.2.3 DCO With 65 Stages Cyclic TDC 102
5.2.4 Summary 104
5.3 Interpolator-based Fine-Tuning Stage Linearity Issue 107
5.3.1 DCO With Interpolator-Based Fine-Tuning Stage 107
5.3.2 DCO Without Fine-Tuning Stage 111
Chapter 6 Conclusion and Future Works 114
6.1 Conclusion 114
6.2 Future Works 115
References 117

[1]Rong-Jyi Yang and Shen-Iuan Liu, “A 40-550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm, “ IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 361-373, Feb. 2007.
[2]Chao-Wen Tzeng, Shi-Yu Huang and Pei-Ying Chao, “Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 621-630, March 2014.
[3]許家綾, “A Template-Based Layout Automation Tool for PLL Circuits,” 國立中央大學電機工程學系碩士論文, Jul. 2011.
[4]Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee, “An all-digital phase-locked loop (ADPLL)-based clock recovery circuit, “ IEEE Journal of Solid-State Circuits, vol. 34, no. 8, pp. 1063-1073, Aug. 1999.
[5]Terng-Yin Hsu, Chung-Cheng Wang, and Chen-Yi Lee, “Design and analysis of a portable high-speed clock generator, “ IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, no. 4, pp. 367-375, Apr. 2001.
[6]Duo Sheng, Ching-Che Chung, and Jhih-Ci Lan, “A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications,” in Proceedings of International Asia Symposium on Quality Electronic Design (ASQED), Jul. 2012, pp. 123-127.
[7]Ching-Che Chung and Chen-Yi Lee, “An all-digital phase-locked loop for high-speed clock generation, “ IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 347-351, Feb. 2003.
[8]Ching-Che Chung and Chiun-Yao Ko, “A fast phase tracking ADPLL for video pixel clock generation in 65nm CMOS technology, “ IEEE Journal of Solid-State Circuits, vol. 46, no. 10, pp. 2300-2311, Oct. 2011.
[9]Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, and Hong-June Park, “An interpolating digitally controlled oscillator for a wide-range all-digital PLL,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 9, pp. 2055-2063, Sep. 2009.
[10]Hsuan-Jung Hsu and Shi-Yu Huang, “A low-jitter ADPLL via a suppressive digital filter and an interpolation-based locking scheme,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 1, pp. 165-170, Jan. 2011.
[11]Takamoto Watanabe and Shigenori Yamauchi, “An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time, ” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 198-204, Feb. 2003.
[12]Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, and Hyun-Kyu Yu, “A 4-GHz all digital PLL with low-power TDC and phase-error compensation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 8, pp. 1706-1719, Aug. 2012.
[13]Ching-Che Chung, Duo Sheng, and Wei-Siang Su, “A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices, “ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2013.
[14]Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications, “ in Proceedings of 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2006, pp. 105-108.
[15]Mair, H. and Liming Xiu, “An Architecture of High-Performance Frequency and Phase Synthesis,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 835-846, June 2000.
[16]Liming Xiu and Zhihong You, “A “flying-adder” architecture of frequency and phase synthesis with scalability,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, Oct. 2002.
[17]Gang-Neng Sung, Szu-Chia Liao, Jian-Ming Huang, Yu-Cheng Lu, and Chua-Chin Wang, “All-Digital Frequency Synthesizer Using a Flying Adder” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 8, pp. 597 – 601, Aug. 2010.
[18]Wei Liu, Wei (Ruth) Li, Peng Ren, Chinglong Lin, Shengdong Zhang, and Yangyuan Wang, “A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO,” IEEE Journal of Solid-State Circuits, vol. 45, no. 2, pp. 314-321, Feb. 2010.
[19]Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, and An-Yeu Wu, “A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 6, pp. 430-434, Jun. 2010.
[20]Chao-Ching Hung and Shen-Iuan Liu, “A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 6, pp. 321-325, Jun. 2011.
[21]Sebastian Höppner, Stefan Haenzsche, Georg Ellguth, Dennis Walter, Holger Eisenreich, and René Schüffny, “A fast-locking ADPLL with instantaneous restart capability in 28-nm CMOS technology,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 60, pp. 741-745, Nov. 2013.
[22]John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, and Manjusha Shankaradas, “Self-biased high-bandwidth low-Jitter 1-to-4096 multiplier clock generator PLL,” IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1795-1803, Nov. 2003.
[23]Davide De Caro, “Glitch-free NAND-based digitally controlled delay-lines,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no.1, pp. 55-66, Jan. 2013.
[24]Ching-Che Chung, Duo Sheng, and Wei-Da Ho, “A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2012.
[25]Ching-Che Chung, Duo Sheng, and Yang-Di Lin, “An all-digital clock and data recovery circuit for spread spectrum clocking applications in 65nm CMOS technology,” in Proceedings of International Asia Symposium on Quality Electronic Design (ASQED), Jul. 2012, pp. 91-94.
[26]Ching-Che Chung, Chiun-Yao Ko, and Sung-En Shen, “Built-in self-calibration circuit for monotonic digitally controlled oscillator design in 65-nm CMOS technology,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 3, pp. 149-153, Mar. 2011.
[27]Shweta Shah, Nazanin Mansouri and Adrian Nunez-Aldana, “Pre-layout estimation of interconnect lengths for digital integrated circuits,” in Electronics, Communications and Computers, 2006. CONIELECOMP 2006. 16th International Conference on, Feb. 2006, p. 38.
[28]IEEE Std 1497-2001, “IEEE standard for standard delay format (SDF) for the electronic design process,” 2001.
[29]IEEE Std 1481-1999, “IEEE standard for integrated circuit (IC) delay and power calculation system,” 1999.
[30]R. Macys and S. McCormick, “A new algorithm for computing the “Effective Capacitance” in deep sub-micron circuits,” in Proceeding of the IEEE Custom Integrated Circuits Conference, June 1998, pp. 313-316.
[31]L. Wei, D. J. Frank, L. Chang, and H.-S. P. Wong, “A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects,” in Proceeding of International Electron Devices Meeting (IEDM), Dec. 2009, pp. 917-920.
[32]J. Qian, S. Pullela, and L. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 12, pp. 1526-1535, Dec. 1994.
[33]J. E Croix and D. E Wong, “A Fast and Accurate Technique to Optimize Characterization Tables for Logic Synthesis,” in Proceedings 34th Design Automation Conference, pp. 337-340, Jun. 1997.
[34]G. Yu, Y. Wang, H. Yang, and H. Wang, “Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting,” IET Circuits, Devices & Systems, vol. 4, no. 3, pp. 207-217, May 2010.
[35]R. TRIHY, "Addressing library creation challenges from recent liberty extensions," in Proceedings of the 45th Annual Design Automation Conference, Jun. 2008 pp. 474-479.
[36]Tariq El Motassadeq, "CCS vs NLDM comparison based on a complete automated correlation flow between PrimeTime and HSPICE, " in Electronics, Communications and Photonics Conference (SIECPC), 2011 Saudi International, pp. 1–5, Apr. 2011.
[37]Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Dasgupta S. and Bulusu Anand, "An accurate current source model for CMOS based combinational logic cell," in Proceedings of the 13th International Symposium on Quality Electronic Design (ISQED), pp. 561-565, Mar. 2012.
[38]Baljit Kaur, Sandeep Miryala, S.K.Manhas and Bulusu Anand, "An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies," in Proceedings of the 14th International Symposium on Quality Electronic Design (ISQED), pp. 665-669, Mar. 2013.
[39]R. Goyal and N. Kumar (Cadence), "Current Based Delay Models: A Must for Nanometer Timing," Cadence Design Systems, Inc., 2005.
[40]Ching-Che Chung, and Wei-Cheng Dai, “A referenceless all-digital fast frequency acquisition full-rate CDR circuit for USB 2.0 in 65nm CMOS technology, ” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2011, pp. 217-220.
[41]Terng-Yin Hsu, Chen-Yi Lee, Bai-Jue Shieh and Chung-Cheng Wang, "Method and device for digitally synthesizing frequency." U.S. Patent No. 6,150,892. 21 Nov. 2000.