臺灣博碩士論文加值系統

靜電放電（Electrostatic Discharge, ESD）造成產品損壞的問題一直都是存在的，再加上現今的3C產品都要求輕薄短小，處理器運算速度要越來越快或是越來越省電，所以對於抵抗靜電放電的能力也大不如前。雖然一般的重要元件像是IC在設計的時候會把靜電放電的防護電路設計加在裡面，讓它可以通過測試，但常常單一元件沒問題，整體組裝起來就無法通過靜電放電測試，所以與機構的結合是相當重要的。

　　本論文討論的方向是以IEC 61000-4-2規範下接觸放電測試條件下PCB層級的靜電放電防護設計，首先會探討一個電容式觸控螢幕智慧型手機的實際案例，從它遇到的靜電放電問題開始到最後如何解決，可以得知一個產品可能遇到的靜電放電問題，接著最後設計了一個實驗，把前面所提到的靜電放電防護概念導入，以PCB電路板佈局讓PIC12F629這顆IC具有IEC 61000-4-2 Level 4的保護等級，並且討論地對ESD防護設計的重要性與影響。

The problem of electrostatic discharge (ESD) has always been there. And today''s 3C products require frivolous shortness; speed of central processing unit (CPU) becomes faster and faster or more and more power saving, so the ability of ESD protection is weaker than before. Although ESD protection circuits will be added in important components such as integrated circuit (IC) when manufacturers design them, making the components do ESD test can pass standards. Usually single components are all right, but whole assemble together cannot pass ESD test, the combination with the body is very important.

This paper discusses about ESD protection design of printed circuit board (PCB) layer under the contact discharge condition of standard IEC 61000-4-2. First, the actual case of mobile phone with capacitive touch screen will be discussed. Discussing about its ESD problems and how to solve them finally, we can know the ESD problems which products may met in this case. At last, to design an experiment, importing concepts of ESD protection into PCB layout, making the IC-PIC12F629 has IEC 61000-4-2 Level 4 this ESD protection level, and discuss the importance effect of ESD ground to ESD protection design.

第一章　研究動機與目的 1
1.1　論文大綱 2
第二章　靜電放電之原理簡介與規範 4
2.1　靜電的歷史 4
2.2　靜電發生的原因 5
2.2.1　摩擦帶電 5
2.2.2　感應帶電 7
2.3　靜電放電模式 8
2.3.1　四種放電模式等效電路圖與比較 11
2.4　靜電放電的測試規範 12
2.4.1　靜電放電的測試方法 14
2.5　傳輸線脈衝產生系統 19
2.5.1　時域反射傳輸線脈衝產生系統 19
第三章　靜電放電的防護方法 21
3.1　陶瓷電容 21
3.2　積層式變阻器（MLV） 22
3.3　齊納二極體（Zener Diode） 23
3.4　瞬態電壓抑制二極體（TVS diode） 24
3.4.1　TVS二極體與陶瓷電容比較 24
3.4.2　TVS二極體與基層式變阻器比較 25
3.4.3　TVS二極體齊納二極體 25
3.5　靜電放電防護元件的重要參數 26
第四章　實際案例分析 28
4.1　實際案例背景 28
4.2　靜電放電問題分析 29
4.3　解決對策 32
4.3.1　防堵的改善對策 33
4.3.2　宣洩的對策 33
第五章　靜電放電防護實驗 37
5.1　原始測試電路介紹 38
5.1.1　PIC12F629 38
5.1.2　測試電路架構 38
5.1.3　靜電放電防護元件 40
5.2　測試過程 42
5.2.1　測試電路（D1-D3） 43
5.2.2　測試電路（D4-D8） 47
5.2.3　測試電路（D9-D10） 53
5.2.4　測試電路（D11-D12） 57
5.3　實驗儀器 60
5.3.1　ESD槍 60
5.3.2　Source Meter 62
5.4　實驗結果分析 63
5.4.1　ESD測試電路結果分析 63
5.4.2　瞬態電壓抑制元件分析 63
5.4.2　IC電流－電壓特性曲線分析 64
第六章　結論 67
參考文獻 69

[1] 新安全，2006年第一期，靜電：加油站的無形殺手，網址：http://www.people.com.cn/BIG5/paper2515/16879/1482986.html
[2] Y.-W. Hsiao and Ming-Dou Ker, “A 5-GHz differential low-noise amplifier with high pin-to-pin ESD robustness in a 130-nm CMOS process,” IEEE Trans. on Microwave Theory and Techniques, vol. 57, no. 5, pp. 1044-1053, May 2009. (SCI, EI)
[3] J.-C. Tseng, C.-T. Hsu, C.-K. Tsai, S.-C. Chen, and Ming-Dou Ker, “Board level ESD of driver ICs on LCD panel,” IEEE Trans. on Device and Materials Reliability, vol. 9, no. 1, pp. 59-64, Mar. 2009. (SCI, EI)
[4] Ming-Dou Ker, C.-K. Huang, Y.-W. Hsiao, and Y.-F. Hsieh, “Chip-level and board-level CDM ESD tests on IC products,” Proc. of 2009 IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Suzhou, China, Jul. 6-10, 2009, pp. 45-49.(EI)
[5] Gernot Langguth, Christian Russ, Wolfgang Soldner, Bernhard Stein, and Harald Gossner, “ESD Challenges in Advanced CMOS Systems on Chip,” IC Design and Technology (ICICDT), 2010 IEEE International Conference on.
[6] Ming-Dou Ker, Y.-W. Hsiao, and B.-J. Kuo, “ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology,” IEEE Trans. on Microwave Theory and Techniques, vol. 53, no. 9, pp. 2672-2681, Sep. 2005. (SCI, EI)
[7] Xin Wang, Xiaokang Guan, Siqiang Fan, He Tang, Hui Zhao, Lin Lin, Qiang Fang, Jian Liu, Wang, A., Li-wu Yang, “ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs,” Industrial Electronics, IEEE Transactions on.
[8] Ming-Dou Ker and C.-C. Yen, “Investigation and design of on-chip power-rail ESD clamp circuits without suffering latchup-like failure during system-level ESD test,” IEEE Journal of Solid-State Circuits, vol. 43, no. 11, pp. 2533-2545, Nov. 2008. (SCI, EI)
[9] D. D. Ward, “Electrostatic discharge,” IEE Seminar on EMC Design, March 1999, pp.4/1-4/8.
[10] http://www.midwestesd.org/aboutesd.html
[11] M. N. O. Sadiku and C. M. Akujuobi, “Electrostatic discharge (ESD),” IEEE Potentials, Vol. 22, Dec. 2003-Jan. 2004, pp.39-41.
[12] Henry W. Ott, “Electromagnetic Compatibility Engineering”, John Wiley & Sons, in press, 1993.
[13] 黃乙上，高速印刷電路板中靜電放電現象之理論與實驗探討，中山大學碩士蟹，2003。
[14] 柯明道，積體電路之靜電放電防護設計特論講義，2011。
[15] Juin J. Liou, “Electrostatic Discharge (ESD) Protection of Integrated Circuits: Overview, Testing, Modeling, Design, RF Optimization, and Simulation” 2011.
[16] 蔡鎮，液晶顯示器模組靜電放電測試方法研究，逢甲大學電子工程系碩士論文，2006。

[17] IEC 61000-4-2, Electromagnetic Compatibility (EMC), Part 4. Testing and Measurement Techniques–Section 4.2 Electrostatic Discharge Immunity Test, 2008.
[18] 詹奕，高速位系統中靜電放電保護元件之研究，中山大學碩士蟹，2005。
[19] 金麗，TVS二極體產品特點，典亮科技有限公司。
[20] 蔡瑞明，智慧型手機之電容式觸控銀幕的靜電防護分析與改善，逢甲大學資訊電機工程碩士在職專班碩士蟹，2010。
[21] 陳榮達，電子產品ESD認證測試及防制技術，誠信科技股份有限公司，2003。
[22] Ming-Dou Ker, T.-Y. Chen, T.-H. Wang, and C.-Y. Wu, “On-chip ESD protection design by using polysilicon diodes in CMOS process,” IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 676-686, Apr. 2001. (SCI, EI)
[23] Ming-Dou Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. on Electron Devices, vol. 46, no.1 , pp. 173-183, Jan. 1999. (SCI, EI)