臺灣博碩士論文加值系統

本論文從事WiMAX系統之數位控制振盪器與電壓控制振盪器的設計與實作，並將所研製之數位控制振盪器與電壓控制振盪器應用於鎖相迴路中以探討數位式與類比式控制振盪器對鎖相迴路性能的影響。電壓控制振盪器採用Clapp架構設計，其重要參數量測結果包括頻率可調範圍等於330 MHz，輸出功率等於8.2 dBm，二次諧波抑制等於-18 dBc，增益等於110 MHz/V，以及位移100 kHz之相位雜訊等於-84 dBc，位移1 MHz之相位雜訊等於-115 dBc。所使用的供應電壓為3 V，消耗電流為25 mA。數位控制振盪器之振盪核心電路也是採用Clapp架構設計，數位式頻率控制電路以五位元控制單元實現，其中第一位元至第四位元規劃頻率的粗調(Coarse Tuning)，而第五位元規劃上頻帶(Upper Band)與下頻帶(Lower Band)的選擇。數位控制振盪器使用供應電壓為3 V，消耗電流為25 mA其重要參數量測結果包括頻率可調範圍等於60 MHz，輸出功率等於4.5 dBm，二次諧波抑制等於-14 dBc/Hz，增益等於12 MHz/V，以及位移100 kHz之相位雜訊等於-87 dBc，位移1 MHz之相位雜訊等於-110.5 dBc/Hz。論文最後使用自行研發之兩振盪器搭配Peregrine Semiconductor所生產的整數式鎖相迴路晶片PE3336進行鎖相迴路整體模擬與量測，評估電壓控制振盪器與數位控制振盪器對鎖相迴路性能的影響。數位控制振盪器因低增益的特性而比電壓控制振盪器抑制鎖相迴路頻帶內的相位雜訊7 dBc/Hz。

The digital-controlled oscillator (DCO) and the voltage-controlled oscillator (VCO) for WiMAX applications are designed and implemented in this thesis. The developed DCO and VCO are used in a phase-locked loop (PLL) for the evaluation of PLL’s performance adopting digital- or analogy- controlled oscillator. The design of VCO is based on Clapp oscillator. The measured results of VCO include that the frequency tuning range is 330 MHz, the output power is 8.2 dBm, the 2nd harmonic suppression is -18 dBc, the gain is 110 MHz/V, as well as the phase noise is -84 dBc at 100 kHz offset and -115 dBc at 1 MHz offset, respectively. The supply voltage is 3 V and the consumed current is 25 mA. The design of DCO is also based on Clapp. The digital frequency-controlled circuit is performed using 5-bit controlled unit. The first bit to forth bit are designed for the frequency coarse tuning, and the fifth bit is designed for the selection of upper band or lower band. The supply voltage of DCO is 3 V and consumed current is 25 mA. The measured results of DCO include that the frequency tuning range is 60 MHz, the output power is 4.5 dBm, the 2nd harmonic suppression is -14 dBc, the gain is 12 MHz/V, as well as the phase noise is -87 dBc at 100 kHz offset and -110.5 dBc at 1 MHz offset, respectively. In the last stage of this thesis, the developed DCO and VCO are applied into the integer-N PLL PE3336 providing Peregrine Semiconductor to investigate the performance of PLL. The DCO has been suppressed the phase noise in the bandwidth of PLL by 7 dBc/Hz when compared to the VCO due to the DCO’s low gain.

摘 要 ………………………………………………………… i
ABSTRACT ………………………………………………………… ii
誌 謝 ………………………………………………………… iii
目 錄 ………………………………………………………… iv
表 目 錄 ………………………………………………………… v
圖 目 錄 ………………………………………………………… vi
第 一 章 緒論…………………………………………………… 1
第 二 章 數位控制振盪器及電壓控制振盪器設計
2.1 振盪器………………………………………………… 7
2.1.1 振盪器的架構及基本原理…………………………… 7
2.1.2 相位雜訊……………………………………………… 10
2.2 電壓控制振盪器……………………………………… 20
2.2.1 電壓控制振盪器原理與介紹………………………… 20
2.2.2 電壓控制振盪器設計與實作………………………… 22
2.3 數位控制振盪器……………………………………… 26
2.3.1 數位控制振盪器原理與介紹………………………… 26
2.3.2 數位控制振盪器設計與實作………………………… 30
第 三 章 鎖相迴路採用數位控制振盪器以及電壓控制振盪器評
估其關鍵參數
3.1 鎖相迴路……………………………………………… 36
3.2 鎖相迴路之模擬與量測……………………………… 46
3.2.1 整合模擬……………………………………………… 47
3.2.2 量測結果與討論……………………………………… 50
第四章 結論…………………………………………………… 55
參考文獻 ………………………………………………………… 56

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