臺灣博碩士論文加值系統

近年來，腦機介面(BCI)蓬勃發展。這類的介面使人可以經過大腦直接控制機器。為了增加此類介面的發展性，以及其運作的穩定性、正確性，即時的擷取到乾淨的腦電訊號是個重要的課題。
此研究主要設計高效能且低功耗的腦機介面系統晶片，整合腦波獨立通道成分析處理器以及腦波特徵識別處理器。腦波訊號取得後經由獨立成份分析處理，再將腦波特徵做即時性的辨識。本研究之晶片設計所採用的是線上遞迴獨立通道成分分析演算法，此演算法提供一種遞迴歸納最小平方近似之線上分析，其特點是一次運算只利用每個通道的一個取樣訊號即可做訓練，其輸出延遲短。比起先前的演算法，不需要做大量的資料暫存，也更具有資料處理的即時性，更適合以晶片的方式來呈現。然而，系統運算過程中必須要大量且重複使用奇異值分解來完成矩陣逆運算。由於奇異值分解為整個系統中運算量最為龐大的處理單元，在高精準度和即時輸出的前提下，奇異值分解的運算時間和效能都會直接影響系統之結果。此整合腦機介面與線上遞迴獨立通道成分分析處理器已被我們實現於TSMC 40nm COMS 製程，其核心所占的面積為975×975 μm2。此晶片已透過Agilent 93000 SoC tester完成功能測試，在100M Hz操作頻率與0.9伏核心電壓之下，功率消耗為10.895 mW。經由此晶片的處理，每個腦波訊號能於其取樣後的0.0078125秒內及時得到分離乾淨的腦波訊號。

Recently, brain computer interfaces (BCIs) are developed to control machines through EEG directly. In order to enhance the feasibility, reliability, and accuracy of BCIs, EEG signals used for BCI applications should be acquired from human without artifacts in real-time.
This thesis aims to design an effective and low power system on chip (SoC) of multi-channel EEG signal processor for real-time brain-computer interface (BCI) system. The architecture of the SoC comprises an independent component analysis (ICA) processor with a brain wave identity processor based on canonical correlation analysis (CCA) algorithm. Biomedical signals acquired from front-end sensor modules will be processed in ORICA processor and brain wave identity processor in real-time. In this thesis, a chip was designed based on an online recursive ICA (ORICA) algorithm, which provided an online analysis for recursive least square approximation. This type of ICA features that the output delay can be reduced and the capacity to train data by using a single sample signal extracted from each channel. Compared with other algorithms, ORICA enables real-time data processing, implemented on a chip, and does not require a lot of temporary data storage. However, the singular value decomposition (SVD) processor is widely used to complete the matrix inverse calculation during the system operation in this work. Because the SVD processor spends the most massive amount of computation in the whole system, its computation time and performance will directly affect the result of the system on the premise of the real-time and high accuracy requirements. The System-On-Chip design proposed in this thesis was implemented by using TSMC 40 nm CMOS technology. The core area of the chip is 975*975 μm2. The performance evaluation is done through Agilent 93000 SoC tester. The result shows that the power consumption is 10.895mW with 100 MHz operation frequency and 0.9 V core power. The separated EEG signals are acquired in 0.0078125s after each EEG sample. This work includes a high accuracy ICA processing and a brain wave identification to provide a more accurate EEG information extraction to various BCI systems in real-time.

摘要 i
Abstract ii
致謝　　　 iv
List of Tables vii
List of Figures viii
Chapter 1 Introduction 1
1.1 Electroencephalography 1
1.2 The Motivations for an Chip implementation of Real-time EEG System based on ORICA 7
1.3 Scope and Contributions 8
1.4 Organization of the Thesis 9
Chapter 2 Algorithms 11
2.1 Algorithm of On-line Recursive ICA 11
2.2 Algorithm of Canonical Correlation Analysis 16
2.3 Algorithm of Singular Value Decomposition 17
2.3.1 Iterative Decomposition of Angle of Rotation 21
2.3.2 Scale-factor 22
Chapter 3 System Architecture 24
3.1 Overall Architecture of the ORICA Processor 26
3.1.1 Preprocessing Unit 28
3.1.2 ORICA training Unit 31
3.2 Shared Resource Unit 39
3.2.1 SVD 39
3.2.2 Floating Matrix Multiplier Unit 50
Chapter 4 Chip Implementation 53
4.1 Chip Design Flow 53
4.1.1 Logic Synthesis and Design Constrains 55
4.1.2 Chip IO Definition 56
4.1.3 SOC Encounter Design Flow 58
4.1.4 DRC and LVS Verification 62
4.1.5 DFM Verification 64
4.2 Chip Layout and Specification 64
4.3 Chip Tape-out and Testing 66
Chapter 5 Experimental Result 68
5.1 Performance Analysis of the 8-Channel ORICA Processor 68
5.1.1 Simulation Result of Simulated EEG Patterns 70
5.1.2 Simulation Result of the Real EEG Patterns 75
5.2 Comparison 80
Chapter 6 Conclusion 84
6.1 Conclusion 84
Reference 86

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