|
[1] Jim Dunning, Gerald Garcia, Jim Lundberg, and Ed Nuckolls, “An ALL-Digital Phase-Locked Loop with 50-cycle Lock Time Suitable for High Performance Microprocessors,” IEEE Journal of Solid-State Circuits, Vol.30, no.4, pp.412-422, Apr. 1995. [2] Shyh-Jye Jou, Ya-Lan Tsao and I-Ying Yang. “An All Digital Phase-Locked Loop with Modified Binary Search of Frequency Acquisition,” Electronics, Circuits and Systems, 1998 IEEE International Conference on, vol.2, pp. 195-198, 1998. [3] Jen-Shiun Chiang and Kuang-Yuan Chen, “The Design of an All-Digital Phase-Locked Loop with Small DCO Hardware and Fast Phase Lock,” IEEE Transactions On Circuits and Systems-Ⅱ: Analog And Digital Signal Processing, vol.46, NO.7 July 1999. [4] Kuo-Hsing Cheng and Yu-Jung Chen, “ A Novel All Digital Phase Locked Loop(ADPLL)with Ultra Fast Locked Time and High Oscillation Frequency, ”Dept. of Electrical Engineering, Tarnkam University, TaipeiHsien,Taiwan ,R.O.C,2001 IEEE. [5] Jin-Jer Jong, Chen-Yi Lee, ”A Novel Structure for Portable Digitally Controlled Oscillator,” Dept. of Electronics Engineering, National Tung University,1001, University Road, Hsinchu 300, Taiwan, R.O.C, 2001 IEEE. [6] Lai-Kan Leung, Cheong-Fat Chan, and Oliver Chiu-Sing Choy, “A GIGA-HERTZ COMS DIGITAL CONTROLLED OSCILLATOR,” Department of Electronic Engineering, The Chinese University of Hong Kong, 2001 IEEE. [7] EPFL Swiss Federal Institute of Technology, “Low-Power Digital PLL with One Cycle Frequency Lock-In Time for Clock Syntheses up to 100 MHz Using 32,768 Hz Reference Clock,” Department of Electrical Engineering, DE-LEG, 1015 Lausanne, Switzerland, 1996 IEEE. [8] Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee, ”An All-Digital Phase-Locked Loop(ADPLL)-Based Clock Recovery Circuit,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 8, AUGUST 1999 [9] S. R. Abdollahi, S. Kiaei, B. Bakkaloglu, S. M. Fakhraie, R. anvari and S. E. Abdollahi, “AN ALL-DIGITAL PROGRAMMABLE DIGITALLY- CONTROLLED-OSCILLATOR(DCO)FOR DIGITAL WIRELESS APPLICATIONS,” University of Tehran, 2002 IEEE. [10] Thomas Oisson and Peter Nilsson, “An all-Digital PLL Clock Multiplier,” Dept. of Electroscience, Lund University. [11] David J. Foley, and Michael P. Flynn, “CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator,” IEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001. [12] Heung-Gyoon Ryu and Hyun-Seok Lee, “ANALYSIS AND MINIMIZATION OF PHASE NOISE OF THE DIGITAL HYBRID PLLL FREQUENCY SYNTHESIZER,” IEEE Transactions on Consumer Electronics, Vol. 48, No. 2, MAY 2002. [13] Takamoto Watanabe and Shigenori Yamauchi, “An All-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time,” IEEEJOURNAL OF SOLID- STATE CIRCUITS, VOL. 38, VOL. 38, NO. 2, FEBRUARY 2003. [14] G. B. Lee, P. K. Chan and L. Siek, “A COMS Phase Frequency Detector for Charge Pump Phase-Locked Loop,” Nanyang Technological University, School of Electrical University, 1999 IEEE. [15] Won-Hyo Lee, Jun-Dong Cho, Sung-Dae Lee, “A High Speed and Low Power Phase-Frequency Detector and Charge-pump”, Asia and South Pacific -Design Automation Conference, pp.269 -272 , 1999. [16] Chi-Cheng Cheng, “The Analysis and Design of All-Digital Phase-Locked Loop(ADPLL),” Master Thesis, National Chiao Tung University, 2001. [17] 黃嘉慶, “The Design and Analysis of the All-Digital CMOS Delay-Locked Loop,” Master Thesis, National Chung Hsing University, 2000. [18] 游榮豪, “High Speed All Digital Phase-Locked Loop,” Master Thesis, National Chung Hsing University, 2001. [19] 郭隆質, “1.5V 900MHz CMOS Phase Locked-Loop,” Master Thesis, National Chung Hsing University, 2000. [20] Neil H. E. Weste and Kamran Eshraghian, “Princhples of CMOS VLSI Design : A Systems Perspective 2/E,” 2000. [21] 鄭為全, “Analysis and Design of the All-Digital Phase-Locked Loop, Master Thesis,” National Taiwan University ,1997. [22] 陳光原, The Design and Implementation of a 3.3v 400MHz All Digital Phase-Locked Loop, Master Thesis, Tamkung University,1997. [23] 楊怡英, The implementation and analysis of an All Digital Phase Locked-Loop, Master Thesis, National Central University,1997 [24] 盛鐸, An All Digital Phase Locked-Loop(ADPLL) with Fast Lock-In Time─Analysis, Implementation and Application, Master Thesis, National Chung Cheng University, 1999 [25] 許騰尹, The Study of All Digital Phase Locked-Loop(ADPLL) and its Applications, Dissertation Thesis, National Chiao Tung University, 1999 [26] T.-Y. Hsu, B.-J. Shieh, and C.-y. Lee,“An all-digital phase-locked loop (ADPLL)-based clock recovery circuit,”IEEE J. of Solid-State Circuits, vol.34,no. 8, pp. 1063~1073, August 1999. [27] 曹亞嵐, All Digital Phase Locked-Loop, Master Thesis, National Central University, 1996. [28] Roland E. Best, Phase-Locked Loop : Design, Simulation, & Applications, Third Edition, McGraw-Hall Inc., 1993.
|