臺灣博碩士論文加值系統

幾乎大家現在擁有至少一個無線產品，例如手機、無線網路(WLAN)、藍芽等等。由於爆炸性的大眾化，許多研發人員在世界各地努力減少成本，縮減大小，使這些無線產品有最小功率消耗和增加效能。以滿足這些要求，使用金屬氧化半導體(CMOS)完全整合成系統晶片(SOC)製作包括RF電路是其中一種最有吸引力的解決方式。 然而，電路設計師面對困難的挑戰來發展金屬氧化半導體集成射頻解決方案，因為金屬氧化半導體的速度或功率效能是不如其他技術如雙極性電晶體和砷化镓(GaAs)，並且有損矽基板的被動元素導致不足的效能。
本文提出一個精巧，線性化方式適合用到金屬氧化半導體功率放大器(PA)。它打算用於高速率的無線系統16-QAM信號，它要求更大的功率放大器線性度。一個台積電(TSMC) 0.18μm互補金氧半導體的一個最佳化設計AB類(Class AB)3.5 GHz功率放大器是提出。一個平坦的區域與非常低3階係數或許用兩個或多個FET結合，以消除負數的3階係數，其中一個為飽和的電晶體與第二個在三極管的電晶體的正值3階係數。 如果共源極電晶體在飽和時被偏壓在某一Vgs電壓，而第二個電晶體也被強制進入三極管區域在相同的Vgs電壓，經由堆疊成為疊接電晶體和然後被相加的二電晶體電流路徑以達成從中消除第3階係數。3.5 GHz功率放大器傳送14.2 dBm的輸出功率到50Ω負載時互調變失真(IMD)為-44 dBc且增益為9.96 dB 和附加功率效率(PAE)為7.17%在2V電源下。

Almost everyone now owns at least one wireless product, such as a cellular phone, WLAN, Bluetooth, etc. Due to this exploding popularity, many researchers around the world striving to reduce cost, decrease size, minimize power consumption and increase performance of these wireless products. To satisfy these requirements, a CMOS fully integrated system-on-chip (SOC) implementation including the RF circuits is one of the most attractive solutions. However, circuit designers face difficult challenges to develop CMOS integrated RF solutions because CMOS speed/power performance is inferior to other technologies such as BJT and GaAs, and the lossy silicon substrates cause poor performance in the passive elements.
This paper presents a compact, linearization method suited to CMOS power amplifiers. It is intended for use in a high bit-rate wireless system signaling with 16-QAM, and using every channel in each cell, it demands higher power amplifier linearity. An optimized design of a TSMC 01.8μm CMOS class AB 3.5 GHz power amplifier is presented. A flat region with very low may be synthesized with two or more FETs, by canceling the negative , of one FET in saturation with the positive of a second FET in triode. If common-source FET is biased in saturation at some a second FET may be forced into the triode region at the same , by stacking on it a Cascode FET, and the two FET currents path then summed to achieve the cancellation in the 3rd-orderoefficient. The 3.5 GHz PA delivers 14 dBm of output power to 50Ω load with an IMD of - 44 dBc and an EVM of -16.3 dB and gain of 9..96 dB and PAE of 7.17 % at 2 V supply.

摘　要 i
Abstract ii
誌 謝 iii
目 錄 iv
第一章緒論 1
1.1 研究背景 1
1.2 研究動機及目的 2
1.3 論文架構 5
第二章功率放大器與RF CMOS 製程概述 6
2.1 簡介 6
2.2功率放大器的分類 8
2.3負載線理論 10
2.4 功率等位圓（Constant Power Contour） 14
2.5 RF CMOS 製程概述 18
2.5.1 模型與設計的關係 18
2.5.2 NMOS電晶體 18
2.5.3 MIM 電容 20
2.5.4 電阻 21
2.5.5 螺旋電感 21
2.5.6 鎊線(bondwire)及鎊墊(pad) 23
第三章 功率放大器設計考量 24
3.1功率放大器性能參數 24
3.2放大器的工作穩定性 24
3.3線性度的參數 25
3.4 AM/AM與AM/PM 28
3.5鄰近通道功率比例 29
3.6特性阻抗匹配與微調 31
3.7 負載調整法(Load-Pull Method) 33
3.8 正交分頻多工(OFDM) 36
3.9 誤差向量(Error Vector Magnitude; EVM) 40
第四章 線性功率放大器之設計與模擬 42
4.1簡介 42
4.2 電路架構 43
4.3 直流分析 43
4.4 疊接架構(Cascode) 46
4.5完整的單端電路架構 47
4.6 負回授網路考量 48
4.7匹配網路的設計 49
4.8設計流程 51
4.9模擬結果 51
4.10系統模擬 64
4.11 Layout佈局與設計考量 70
4.12電路規格與文獻的比較 71
第五章 結論與未來展望 73
5.1 結論 73
5.2 未來展望 73
參考文獻 74

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