臺灣博碩士論文加值系統

在這篇碩士論文中，我們提出了一個用於內嵌式記憶體的自我測試電路產生器 BIST for RAm IN Seconds (BRAINS)。這個自我測試電路產生器可以根據記憶體的規格，還有測試的要求來產生可合成的自我測試電路，自我測試電路的啟動信號，驗證自我測試器的信號，及邏輯合成的指令。這個自我測試電路的架構是從我們以前所做的架構更改而來，這個自我測試電路可以提供可程式化的 March 測試演算法，及即時測試。這個自我測試電路產生器也可以根據使用者的調整使所產生的自我測試電路提供記憶體區塊夾雜存取, 錯誤診斷的支援等功能及用來測試數個記憶體元件。
在這個自我測試電路產生器 (BRAINS) 中，我們用了記憶體模型化技巧去描述一個記憶體的運作。記憶體模型化的技巧包括了描述記憶體的輸入和輸出埠 (I/O port)，記憶體的指令 (Command)，記憶體的操作 (task) 及記憶體的時序限制 (Timing limitation)等。使用這個記憶體模型化技巧，這個自我測試電路產生器可以根據這些模性化出來的參數產生相對應的自我測試電路。 因此，我們所提出的自我測試電路產生器可以很輕易的去支援許多複雜而且不同種類的的記憶體架構。
在。在實驗結果中，我們針對了常見的記憶體的架構，包括了靜態記憶體 (SRAM) 和動態記憶體 (DRAM) 產生出自我測試電路，並且估算額外所需要的晶片面積。我們也舉出這個自我測試電路產生器用在兩個工業界的例子，分別是用於不同的靜態記憶體架構，而面積的增加分別為 3.5% 及 4.3%。

A framework for embedded memory built-in self-test (BIST) compilation, called BRAINS (Bist for RAm IN Seconds), is proposed. According to the memory specifications and the test requirements, BRAINS generates the synthesizable BIST code in Verilog HDL, as well as its activation sequence, test bench and synthesis scripts. The architecture for BIST circuits generated by BRAINS is an improved version of our previous work. The new design provides at-speed testing, and programmable March tests. With the user's configuration, the generated BIST circuit can
further provide bank interleaving access, diagnosis support,
and be shared among multiple memory cores. BRAINS generates the
BIST circuit by using the Memory Modeling Techniques. With the
techniques, it is easy for BRAINS to support modern and customized memory architecutres. Two real industry chips for different SRAM architectures are shown as our experimental results. The area overheads are 3.5\% and 4.3\%, repectively.

第一章 序論
第二章 研究背景
第三章 系統架構
第四章 實驗結果
第五章 結論

[1] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, ``A programmable BIST core for embedded DRAM'', IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59--70, Jan.-Mar. 1999.
[2] M.~Marinescu, ``Simple and efficient algorithms for functional {RAM} testing'', in Proc. Int. Test Conf. (ITC), 1982, pp. 236--239.
[3] A.~J. van~de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester, England, 1991.
[4] K.-J. Lin and C.-W. Wu, ``PMBC: a programmable BIST compiler for memory cores'', in Third IEEE Int. Workshop on Testing Embedded Core-Based System-Chips, Dana Point, Apr. 1999, pp. P2.1--P2.6.
[5] C.-F. Wu, C.-T. Huang, and C.-W. Wu, ``RAMSES: a fast memory fault simulator'', in Proc. Int. Symp. Defect and Fault Tolerance in VLSI Systems.
[6] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu,
``Simulation-based test algorithm generation for random access in Proc. IEEE VLSI Test Symp. (VTS), Montreal, Apr. 2000 (to appear).
[7] B.~F. Cockburn and Y.-F.~Nicole Sat, ``Synthesized transparent BIST for detecting scrambled in Proc. Int. Test Conf. (ITC), Oct. 1995, pp. 23--32.
[8] O.~Kebichi and M.~Nicolaidis, ``A tool for automatic generation of BISTed and transparent BISTed RAMs'', in Proc. IEEE Int. Conf. Computer Design (ICCD), Oct. 1992, pp. 570--575.
[9] Rochit Rajsuman, ``RAMBIST builder: A methodology for automatic built-in self-test design of embedded rams'',
in Proc. IEEE Int. Workshop on Memory Technology, Design and
Testing, Aug. 1996, pp. 50--56.
[10] K.~Zarrineh and S.~J. Upadhyaya, ``On Programmable Memory Built-in Self Test Architecture'', in Proc. Design Automation and Test in Europe (DATE), 1999.
[11] K.~Zarrineh and S.~J. Upadhyaya, ``Programmable memory BIST and a new synthesis framework'', in Proc. Int. Symp. Fault Tolerant Computing (FTCS), June 1999, pp. 352--355.
[12] K.~Zarrineh and S.~J. Upadhyaya, ``A NEW Framework for Automatic Generation, Insertion, Verification of Memory Built-in Self Test Unit'', in Proc. VLSI Test Symp (VTS), 1999, pp. 391--396.