臺灣博碩士論文加值系統

電子領域中產品的發展趨勢被要求尺寸縮減、性能提高和整合度提升。本文探討薄膜型黏晶材料主要應用於堆疊式晶片級封裝體(Stacked Chip Scale Package，SCSP)中，實驗重點於堆疊晶片封裝構造中選擇兩種薄膜型黏晶材料DAF(Die Attach Film)與FOW(Film Over Wire)做材料特性與應用表現之探討。
由熱分析與流變結果中發現FOW的填充物含量較多，具有較低的初始反應溫度及適合加工的區間較長且黏度較低，故材料的結構強度與加工性較好。由微結構分析結果指出FOW有緻密均勻的圓形填充物結構，可強化堆疊的強度，其填充物大小約為DAF的1/3，較不傷及晶片表面且提供較佳的流動性。後續製程模擬與可靠性實驗中，薄膜型黏晶材料與相關結構材料(晶片及銲線)接合情形良好，無脫層現象。兩相比較結果顯示FOW可以包覆保護銲線，無損傷現象，而DAF則因為強度不足以致於無法支撐堆疊晶片之間的空間，所以所包覆之銲線遭到上層堆疊晶片的擠壓，產生變形現象。基於以上特性分析與模擬實驗結果，了解FOW較適合作為堆疊晶片封裝的黏晶材料，原因在於其擁有較低的初始反應溫度與較多的緻密均勻大小的填充物，較低的初始溫度搭配有效的製程溫度則可於初期製程貼合使用時，取得較佳的材料成膜性質，應用於製程堆疊時，其均勻大小的填充物比例則可強化樣品堆疊結構。

The trend of the electronics product is required to reduce the package size, improve the performance and advance integration. This thesis discussed that the film type die attach material mainly applied in the stacked chip scale package (SCSP). The experiment chosed two types of film, DAF (Die Attach Film) and FOW (Film over Wire), to discuss the material characteristic and applied representation in the stacked die package structure.
The thermal analysis and Rheology datas showed FOW had more filler content, lower initial reaction temperature, longer working window and better viscosity presentation, it indicated FOW had well structure and workability. By micro structure analysis result presented the small, uniform and circular filler existed in the FOW and the filler size of FOW is 1/3 than DAF, it can enhance structure strength, provide good flow condition and doesn’t damage the die surface. The simulated experiment result showed good adhesion between the interfaces of the related material. No delamination has been observed in both types film packaging. However, DAF had bonding wire damaged issue due to poor structure strength. Based on above material characteristic and experiment simulated result, to understand the cause of preferred FOW to be die attach material in the stacked die package is it had lower initial reaction temperature and more uniform filler content; the lower initial reaction temperature collocate with effective process confition can get well film condition.

總目錄
中文摘要 I
英文摘要 III
誌謝 IV
總目錄 V
表目錄 VII
圖目錄 VIII
第一章 緒論 1
1.1 堆疊晶片構裝技術趨勢簡介 1
1.2 堆疊晶片構裝技術 2
1.3 堆疊晶片構裝研究與未來發展 4
第二章 文獻回顧 5
2.1 堆疊晶片封裝結構 5
2.2 黏晶材料的發展 6
2.3 常見黏晶材料簡介 8
2.3.1 黏晶膠材Spacer Paste 8
2.3.2 薄膜型黏晶材料 9
2.3.3 不同黏晶材料的差異 12
2.4 研究動機與目的 12
第三章 實驗步驟及方法 14
3.1 實驗構想 14
3.2 樣品處理製作 16
3.2.1 樣品結構 16
3.2.2 樣品製作流程 17
第四章 結果與討論 19
4.1 薄膜型黏晶基材特性分析 19
4.1.1 薄膜型黏晶基材採用 19
4.1.2 薄膜型黏晶基材TGA分析 19
4.1.3 薄膜型黏晶基材DSC分析 20
4.1.4 薄膜型黏晶基材Rheology分析 23
4.2 堆疊晶片封裝結構中不同黏晶材料分析 26
4.2.1 黏晶基材微結構分析 26
4.2.2 堆疊晶片封裝結構中黏晶材料微結構分析 27
4.2.3 堆疊晶片封裝結構中包覆銲線能力的觀察 30
4.3 加速試驗對黏晶材料表面黏著的影響 33
4.3.1 超音波掃描式顯微鏡觀察 33
4.3.2 加速試驗-壓力鍋試驗對黏晶材料表面黏著的影響 36
4.3.3 加速試驗-溫度循環試驗對黏晶材料表面黏著的影響 37
第五章 結論 39
參考文獻 43

[1]. B.H., Oh, H.Y., Loo, P.T., Oh, and E.K., Lee “Challenges in Stacked CSP Packaging Technology”, Electronic Materials and Packaging, EMAP 2006. International Conference on, 2006, pp.1-10.
[2]. S.N., Song, and H.H., Tan, P.L., Ong, “Die Attach Film Application in Multi Die Stack Package”, IEEE Electronics Packaging Technology Conference, Vol. 2, 2005, pp.848-852.
[3]. X.L., Cheng,and F., Qian, “Analysis on the Effects of Packaging Materials on Structural Thermal Stress in Stacked Chip Scale Package”, Electronic Packaging Technology, ICEPT 2007. 8th International Conference on, 2007, p.1.
[4]. H.C., Hsu，Y.C., Hsu, H.Y., Lee, C.L., Yeh, and Y.S., Lai, “Application of Submodeling Technique to Transient Drop Impact Analysis of Board-level Stacked Die Packages”, IEEE Electronics Packaging Technology Conference, 2006, pp.412-418.
[5]. Y.M., Cheung, A.C.M., Chong and B., Huang, “Determination of the Interfacial Fracture Toughness of Laminated Silicon Die on Adhesive Dicing Tape from Stud Pull Measurement”, Electronic Materials and Packaging, EMAP 2006. International Conference on, 2006, pp.1-10.
[6]. A.T., Cheung, “Dicing Die Attach Films for High Volume Stacked Die Application”, Electronic Components and Technology Conference, Proceedings. 56th, 2006, pp.1312-1316.
[7]. I., Ahmad, N.N., Bachok, N.C., Chiang, M. Z.M., Talib, M.F., Rosle,
F.L.A., Latip, Z.A., Aziz, “Evaluation of Different Die Attach Film and Epoxy Pastes for Stacked Die QFN Package”, IEEE 9th
Electronics Packaging Technology Conference, 2007, pp.869-873.
[8]. M., Todd, “Material Systems Enable High Density Packaging”, IEEE Proceedings of HDP 07, 2007, pp.1-5.
[9]. X.Q., Shi, Q.J., Yang, J.H.L., Pang,and W., Zhou, “Measurement on Thermal Properties of Solid Films in ElectronicPackages”, 1998 IEEWCPMT Electronics Packaging Technology Conferenc, 1998, pp. 308-312.
[10]. E.J., Vardaman, and L., Matthew, “New Developments in Stacked Die CSPs”, IEEE Proceedings of HDP 04, 2004, pp.29-30.
[11]. S., Takeda,and T., Masuko, “Novel Die Attach Films Having High Reliability Performance for Lead-free Solder and CSP”, IEEE Electronics Components and Technology Conference, 2000, pp.1616-1622.
[12]. M., Rencz, “Thermal Issues in Stacked Die Packages”, IEEE, 21th 　　　　　　　IEEE SEMI-THERM Symposium, 2005, pp.307-312.
[13].　 P., Liu, and L., Cheng, “Thin Film Failure Using an Interface
Delamination Law”, IEEE 1998 IEEWCPMT Electronics Packaging
Technology Conference, 1998, pp.43-48.
[14].　 A.A., Shores, “Thermoplastic Filhs for Adhesive Bonding
　　　Hybridmicrocircuit Substrates”, IEEE, 2006, pp.891-896.
[15]. J., Jang, J., Bae,and K., Lee, “Synthesis and characterization of
polyaniline nanorods as curing agent and nanofiller for epoxy matrix composite”, Elsevier Ltd. All rights reserved.,Vol. 46, No.11, 2006, pp.3677-3684.
[16]. T.L., Hoopman, R.S., Reylek, J.L., Schenz, and K.C., Thompson, “New Film-Type Die Attach Adhesives”, IEEE, 2006, pp.473-479.
[17]. H., Nakayoshi, N., Izawa,and T., Ishikawa “Memory Package with LOC Structureusing New Adhesive Material”, IEEE 1994, pp.575-579.
[18]. 矽品精密股份有限公司(SPIL)，“FOW(Film over wire)獨家專利封裝技術”，台灣專利字號：142309，美國專利字號：US6388313。
[19]. H.H., Jiun, I., Ahmad, A.,Jalar, and G., Omar “Alternative Double Pass DicingMethod for Thin Wafer Laminated with Die Attach Film”, ICSE, 2004, pp.636-641.
[20]. S. C., Kheng, M. Teo, and C., Lee “Assessment of Die Attach Film for Thin Die and SiP Applications” IEMT, 2006, pp.288-293.
[21]. S., Abdullah, S., MohdYusof, I., Ahmad, A., Jalar, and R., Daud “Dicing Die Attach Film for 3D Stacked Die QFN Packages”, Int''l Electronics Manufacturing Technology Symposium, 2007, pp.73-75.
[22]. M., Teo, S.C., Kheng, and C., Lee “Process and Material Characterization of Die Attach Film (DAF) for Thin Die Applications”, IEEE 2006, pp.58-63.
[23]. Jonathan Medding, Roland Stalder, Marcel Niederhauser, Patrick Stoessel “Thin Die Bonding Techniques”, IEEE 2004 IEEE/SEMI Int''l Electronics Manufacturing Technology Symposium, 2004, pp. 31-25.
[24]. T.Y., Tsai, H.C., Chang, W.C., Li, C.P., Teng, and Y.S., Lai “Working Temperature Characterizations for Die Attach Films in Stacked-die Process”, IEEE Int''l Electronics Manufacturing Technology Symposium, 2007, pp.92-95.
[25]. S.W., Wang, and M.C., Yo “4 mil DAF Die Thickness Sawing Capability Study”, IEMT Int''l Electronics Manufacturing Technology, 2006, pp.207-219.
[26]. Karjalainen, P., Tanskanen, J., and Ristolainen, E.O., “Reliability Evaluation Structures for Stacked Thin Dice Packaging”, 53rd Electronic Components and Technology Conference, 2003, pp. 1197-1202.
[27]. Ng, C. C., and Embong, S. S., “Investigation of Sheared Die Using Both Computational Fluid Dynamics and Solid Modeling Techniques”, SEMICON Singapore SEMI Technology Symposium, 2004, pp.115-120.
[28]. Shi, D. and Fan, X., “Wafer-level Film Selection for Stacked-Die Chip Scale Packages”, 57th Electron. Comp. Technol. Conf, 2007, pp.1731-1736.
[29]. C. Paydenkar, A. Poddar, H. Chandra, and S. Harada, “Wafer Sawing Process Characterization for Thin Die (75 micron) Application”, 29th IEEE IEMT Symp., 2004, pp.74-77.
[30]. H. H. Jiun et al, “Effect of Laminated Wafer toward Dicing Process and Alternative Double Pass Sawing Method to Reduce Chipping”, IEEE Trans. Elect. Pkg. Manuf., Vol. 29, No. 1, 2006, pp.17-24.