臺灣博碩士論文加值系統

Author : Manoj Kumar
Title : 20-60V NLDMOS low on-resistance device based on 0.25um BCD process Technology
Department : Computer Science and Information Engineering
Year : 2012
Place : Asia University, Taichung, Taiwan

Thesis for the Degree of Master of Science in Industrial Technology R&D Master Program on Computational Microelectronic


In this thesis, high voltage NLDMOS (20-60V) low on-resistance (Ron) device based on 0.25 um BCD (Bipolar-CMOS-DMOS) technology had been studied. Power management is becoming highly growing market in semiconductor industry. The future growth of power management market is mainly driven by mobile computer market, infrastructure replacement, alternative energy market, and improving efficiency of existing electronics.The birth and evolution of BCD technologies combining power devices, Bipolar and CMOS components, has allowed the realization of complete systems or sub-systems in true single chip solution. However in the BCD process the main challenge is to get DMOS device either n-type or p-type with low on-resistance so that power dissipation should be small. Since in power management we use LDMOS device either for switching or control operation. For switching operation we need NLDMOS device with low on-resistance so that our switching speed will be faster. But there is a tread off between Ron and Breakdown voltage (BVD). As our BVD increases Ron will also increase and vice versa. Also in BCD process we need LDMOS device to be scalable means that the single process flow should cover wide range of BVD. Normally the ideal one is from 20V to 60V.
When we use single process for several voltages range LDMOS the change is only in masking so that we get different pitch (Distance between source and drain contact) for different device. For 20V device pitch will be smallest and for 60V the pitch will be largest. In our work we used small P-Top region in between source and drain to optimize the BVD and Ron. By using P-top region we make use of double resurf concept in this concept when we optimize the dose of P-top with drift region so that there will be completely charge balance. When we get complete charge balance between drift and P-Top the trade-off between BVD and Ron will be maximum. Also to check the ability of the MOSFET to withstand instances of unclamped inductive switching (UIS) is an important performance metric i.e. the ruggedness of the MOSFET. We have performed UIS test to understand the reliability of device in terms of ruggedness.

Keywords : BCD (Bipolar-CMOS-DMOS), High Voltage Device, NLDMOS, P-Top, Drift region, On-resistance (Ron), Breakdown voltage (BVD), UIS, TCADSimulation.

Author : Manoj Kumar
Title : 20-60V NLDMOS low on-resistance device based on 0.25um BCD process Technology
Department : Computer Science and Information Engineering
Year : 2012
Place : Asia University, Taichung, Taiwan

Thesis for the Degree of Master of Science in Industrial Technology R&D Master Program on Computational Microelectronic


In this thesis, high voltage NLDMOS (20-60V) low on-resistance (Ron) device based on 0.25 um BCD (Bipolar-CMOS-DMOS) technology had been studied. Power management is becoming highly growing market in semiconductor industry. The future growth of power management market is mainly driven by mobile computer market, infrastructure replacement, alternative energy market, and improving efficiency of existing electronics.The birth and evolution of BCD technologies combining power devices, Bipolar and CMOS components, has allowed the realization of complete systems or sub-systems in true single chip solution. However in the BCD process the main challenge is to get DMOS device either n-type or p-type with low on-resistance so that power dissipation should be small. Since in power management we use LDMOS device either for switching or control operation. For switching operation we need NLDMOS device with low on-resistance so that our switching speed will be faster. But there is a tread off between Ron and Breakdown voltage (BVD). As our BVD increases Ron will also increase and vice versa. Also in BCD process we need LDMOS device to be scalable means that the single process flow should cover wide range of BVD. Normally the ideal one is from 20V to 60V.
When we use single process for several voltages range LDMOS the change is only in masking so that we get different pitch (Distance between source and drain contact) for different device. For 20V device pitch will be smallest and for 60V the pitch will be largest. In our work we used small P-Top region in between source and drain to optimize the BVD and Ron. By using P-top region we make use of double resurf concept in this concept when we optimize the dose of P-top with drift region so that there will be completely charge balance. When we get complete charge balance between drift and P-Top the trade-off between BVD and Ron will be maximum. Also to check the ability of the MOSFET to withstand instances of unclamped inductive switching (UIS) is an important performance metric i.e. the ruggedness of the MOSFET. We have performed UIS test to understand the reliability of device in terms of ruggedness.

Keywords : BCD (Bipolar-CMOS-DMOS), High Voltage Device, NLDMOS, P-Top, Drift region, On-resistance (Ron), Breakdown voltage (BVD), UIS, TCADSimulation.

DEDICATION i
ABSTRACT ii
ACKNOWLEDGEMENT iv
TABLE OF CONTENT v
LIST OF FIGURES viii
LIST OF TABLES x
CHAPTER 1 1
INTRODUCTION 1
1.1 . HISTORY OF POWER DEVICES 1
1.1.1. Limits of Indivisual Transistors 2
1.1.2. The Integrated Circuit 2
1.1.3. MOSFETs 2
1.1.4. LDMOS (Laterally Diffused Metal oxide Semiconductor Field Effect Transistor) 4
1.2 . EVOLUTION OF BCD (Bipolar CMOS DMOS) and ADVANTAGES 5
1.3 . THESIS MOTIVATION 8
1.4 . THESIS OBJECTIVES 9
1.5 . THESIS OUTLINES 9
CHAPTER 2 10
LDMOS TRANSISTORS AND THEIR ELECTRICAL BEHAVIOR 10
2.1 . GENERAL INFORMATION OF LDMOS TRANSISTOR 10
2.2 .ELECTRICAL BEHAVIOR 12
2.2.1. Breakdown Voltage 15
2.2.1.1.Dielectric Breakdown in Gate Oxide 15
2.2.1.2.Punchthrough Breakdown 15

2.2.1.2.1.Punchthrough Breakdown between souce and drain 15
2.2.1.2.2.Punchthrough Breakdown between souce and substrate 16
2.2.2. On-Resistance 16
2.2.3. Transconductance 17
2.2.4. Threshold Voltage 18
CHAPTER 3 19
SIMULATION METHODOLOGY 19
3.1 . INTRODUCTION OF SIMULATION PLATFORM 19
3.2 . DEVICE GENERATION 20
3.2.1 Tsuprem4 20
3.2.2. Process Simulation 20
3.2.3. Mesh Generation 21
3.2.4. Oxidation 22
3.2.5. Masking 23
3.2.6. STI Isolation Process 23
3.2.7. Diffusion 24
3.2.8. Contact and Metallization 25
3.3 . DEVICE PHYSICS CONSIDERATION 26
3.3.1.Mobility Model 26
3.3.2.Recombination Model 27
3.4 . ADVANTAGES AND LIMITATION OF TCAD TOOLS 28
CHAPTER 4 30
RESULTS AND DISCUSSION 30
4.1 . INTRODUCTION 30
4.2 . NLDMOS DEVICE PROCESS FLOW 30
4.3 . 20-60V DEVICE STRUCTURES AND ELECTRICAL CHARACTERISTICS 32
4.3.1.20V NLDMOS Device 32
4.3.2.30V NLDMOS Device 35
4.3.3.40V NLDMOS Device 37
4.3.4.50V NLDMOS Device 39
4.3.5.60V NLDMOS Device 41
4.4 . EFFECTS OF SMALL P-TOP REGION ON DEVICE CHARACTERISTICS 43
4.5 . COMPARISON OF THIS WORK 45
CHAPTER 5 46
UNCLAMPED INDUCTIVE SWITCHING TEST 46
5.1 . INTRODUCTION 46
5.2 . AVALANCHE FAILURE MECHANISM 46
5.3 . ENERGY AND AVALANCHE CURRENT CALCULATIONS USING UIS 49
5.4 . SUMMARY 51
CHAPTER 6 52
CONCLUSIONS AND FUTURE WORK 52
6.1 .CONCLUSIONS 52
6.2 . FUTURE WORK 52
REFERENCES 53

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