臺灣博碩士論文加值系統

隨著先進的極大型積體電路技術，積體電路的工作速度，晶片尺寸和電路的密集度也相對提升。這意謂我們將來的極大型積體電路將迫切需要低功率，低電壓的技術。同時對一個低電壓的積體電路而言，在閘極氧化層厚度相當薄的情況下，其崩潰電壓也隨之下降。因此，發展低電壓觸發靜電放電保護電路是刻不容緩的課題。
本論文我們提供有關於靜電放電的基本知識與問題，同時提出多種全新的靜電放電防護電路。這些防護電路的實現乃用電腦輔助電路設計及積體電路佈局軟體產生電路佈局，再經由將防護電路實現於國科會晶片製作中心製作，或者是由個別的元件所組成，不然就是利用電腦輔助積體電路模擬軟體來模擬。在這些電路中，我們利用閘流體當作主要的電路元件因為它具有高電流傳導能力和低箝制電壓。並且文獻中的實驗證明這些防護電路都有非常好的靜電放電防護能力。此外，我們發展出嶄新的電路技巧，在不利用元件本身崩潰機制下可達到可調式的觸發電壓。所以我們可以有效的控制防護元件的特性並強化積體電路的防護能力而解決這個嚴重的問題。

As ULSI technology advances, the operation of IC speed, chip size andcircuit density increase. This leads us to believe that future ULSIs willrequire very low-voltage and low-power technology. Meanwhile for a low-voltage IC, the gate oxide thickness is rather thin, its gate oxide breakdown voltage
reduces. Therefore it is important to develop a low-voltage trigger electrostatic discharge (ESD) protection circuits.
In this thesis we provide an understanding of the basic knowledge and issues related to ESD and propose several novel ESD protection circuits. These circuits were designed by computer-aided IC layout software and fabricated through National Science Council Chip-Implementation-Center, consisted of discrete componets, or simulated by computer-aided IC simulation software. In these designs we use an SCR structure as main circuit element because of its high current conducting ability and low holding voltage. The excellent ESD protection capability of the circuits was also verified by experimental data. In addition, we develop new techniques to tune the trigger voltage without breakdown mechanism. With these circuits, we can effectively control the characteristics of ESD protection device with high ESD robustness to solve the serious ESD stress problem for future generations of ICs.

Abstract
Acknowledgement (In Chinese)
1 Introduction 1
1.1 Why We Need ESD Protection? ------------------------ 1
1.2 Overview of This Thesis ---------------------------- 6
2 Physics and Operation of ESD Protection Circuit Elements 7
2.1 Introduction --------------------------------------- 7
2.2 Self-Heating Effect -------------------------------- 7
2.3 NMOS Operation in Snapback ------------------------- 10
2.4 SCR Operation in Snapback -------------------------- 15
2.5 Discussion ----------------------------------------- 19
3 ESD Testing 23
3.1 ESD Testing Models --------------------------------- 23
3.2 ESD Technology Benchmarking ------------------------ 27
3.3 Considerations for I/O Circuit Protection ---------- 28
3.3.1 Robustness ------------------------------------- 28
3.3.2 Effectiveness ---------------------------------- 29
3.3.3 ESD Failure Threshold --------------------------- 30
3.3.4 Whole-chip ESD protection ----------------------- 31
4 ESD Design Concepts 33
4.1 ESD Design Synthesis and Network ------------------- 33
4.2 Resistor Ballasting -------------------------------- 35
4.3 MOSFET Gate-Coupling Methods ----------------------- 36
4.3.1 The Gate Modulation Technique ------------------ 36
4.3.2 Implementation of Gate Modulation -------------- 48
4.4 Substrate-Triggering Techniques -------------------- 43
4.5 SCR Techniques ------------------------------------- 44
4.6 Diode-Based Techniques ----------------------------- 45
5 Novel ESD Protection Schemes 46
5.1 A Novel Zener-Diode-Triggering SCR ------------------ 46
5.1.1 Introduction ----------------------------------- 46
5.1.2 Circuit Configuration and Operating Principle -- 47
5.1.3 Experimental and Simulation Results ------------- 50
5.1.4 Discussion ------------------------------------- 52
5.2 A Novel Diode-Chain Triggering SCR ---------------- 53
5.2.1 Introduction ----------------------------------- 53
5.2.2 Circuit Configuration and Operating Principle -- 53
5.2.3 Experimental and Simulation Results ------------ 55
5.2.4 Discussion ------------------------------------- 61
5.3 A Novel Punchthrough MOSFET Triggering SCR --------- 61
5.3.1 Introduction ----------------------------------- 61
5.3.2 Device Physics of Punchthrough ----------------- 63
5.3.3 Circuit Configuration and Operating Principle --- 67
5.3.4 Experimental Results ---------------------------- 71
5.3.5 Applications for Whole-Chip ESD Protection ------ 76
5.3.6 Discussion -------------------------------------- 82
5.4 Temperature Effects -------------------------------- 83
5.4.1 Introduction ------------------------------------ 83
5.4.2 Device Physics of SCR-type SCR ------------------ 85
5.4.3 Experimental Results ---------------------------- 88
5.4.4 Discussion -------------------------------------- 95
5.5 Comparsion with Other ESD Protection Circuits 95
6 Conclusion 97
Bibiohraphy 99
Author (In Chinese) 105
Publication List 106

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