[1] 原榮、鄔文杰、陳積德、宋馭民、劉正瑜,「光纖通訊系統原理與應用」,新文京開發出版股份有限公司,民國 91 年,初版。
[2] 陳聖文,「具自動功率控制 2.5Gb/s 與 5Gb/s 互補式金氧半雷射二極體驅動電路之設計」,碩士論文,國立高雄應用科技大學,2012。[3] 楊舜量,「5-Gb/s 與 10-Gb/s 互補式金氧半光接收前端電路之設計」,碩士論文,國立高雄應用科技大學,2012。[4] 馮國璋,光纖到家市場攻防戰起 E-PON/G-PON 兩強對峙,新通訊元件雜誌,84 期,2008 年。
[5] Z. Gu, A. Thiede, and R. Tao, “CMOS Wideband Amplifier with an Active Shunt Peaking Technique,” Joint Symposium on Opto-&Microelectronic Devices and Circuits, Wuhan/China, 2004.
[6] 盧建君,「光通訊接收端轉阻放大器之設計與製作」,碩士論文,國立交通大學,2007。[7] W-S. Oh, K-Y. Park, and S-Y. Lee, “A 4-CH 10-Gb/s CMOS VCSEL Driver Array with Adaptive Optical Power Control,” IEEE Advanced Communication Technology, Vol. 1, pp. 826-829, Feb. 2010.
[8] A. S. Sedra, and K. C. Smith, 林浩雄、曹恆偉、陳建中、郭建宏 譯,「微電子電路」,台北圖書,2005。
[9] B. Razavi ,「 類 比 CMOS 積 體 電 路 設 計 ( 修 訂 版 ) 」, 李 泰 成 審 校, McGraw-Hill,2005。
[10] 劉深淵、楊清淵,「鎖相迴路」,滄海書局,民國 100 年,初版。
[11] 蕭培墉、吳孟賢,「Hspice 積體電路設計分析與模擬導論」,東華書局,中華民國 96 年 6 月。
[12] 周宗宜,「三十億與五十億位元互補式金氧半光接收前端電路之設計」,碩士論文,國立高雄應用科技大學,2011。[13] X. Zhang, P. Miao, L. Tian, Y-M. Chen, Y-T. Lee, and B-K. Jeong, “Design of Lower Power 4×10Gb/s VCSEL Driver Array,” IEEE MTT-S International, pp. 1-3, Sept. 2012.
[14] D. Zai, Y-M. Chen, L. Tian, and L. Zhang, “Design of a 10-Gb/s Laser Diode Voltage Driver in 0.18μm CMOS Technology,” IEEE MTT-S International, pp. 1-4, Sept. 2012.
[15] R. Annen, “Low Power and Low Noise VCSEL Driver Chip for 10-Gb/s Applications,” Lasers and Electro-Optics Society, Vol.1, pp. 312-313, 2004.
[16] T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, and H. Onodera, “A 16Gb/s Laser Diode Driver with Interwoven Peaking Inductors in 0.18µm CMOS,” IEEE Custom Integrated Circuit Conference, pp. 19-22, Sept. 2010.
[17] 劉柏鋐,「偽隨機二元序列產生器與可變頻段電壓控制振盪器之設計」,碩士論文,國立高雄應用科技大學,2013。[18] N. Quadir, P. Ossieur, and P. D. Townsend, “A 56Gb/s PAM-4 VCSEL Driver Circuit,” Signals and Systems Conference (ISSC 2012), IET Irish, pp. 1-5, Jun 2012.
[19] C-M. Tsai, and M-C. Chiu, “A 10Gb/s Laser-Diode Driver with Active Back-Termination in 0.18μm CMOS,” Solid-State Circuits Conference (ISSCC 2008), pp. 222-608, Feb. 2008.
[20] H-K. Kim, J-J. Lee, J-K. Jung, and J-W. Burm, “A 8 Gb/s 4-PAM Transmitter in 0.18μm CMOS Technology,” SoC Design Conference (ISOCC 2008), Vol. 3, pp. III.17-III.18, Nov. 2008.
[21] K. Farzen, and D. A. Johns, “A CMOS 10-Gb/s Power-Efficient 4-PAM Transmitter,” IEEE Journal of Solid-State Circuit, Vol. 39, Mar. 2004.
[22] J. L. Jeong, and J. Burm, “A CMOS 3.2 Gb/s 4-PAM Serial Link Transceiver,” International SoC Design Conference (ISOCC 2009), pp. 408-411, 2009.