臺灣博碩士論文加值系統

本論文研究是在0.18微米製程技術下研究700伏特橫向雙擴散金氧半場效電晶體功率元件，有別於一般0.5um/1um BCD製程，對整合低壓電路更能提高效率節省成本。搭配Synopsys TCAD模擬、實驗結果、元件佈局等，微調製程參數來得到一低導通電阻的700伏特功率元件。
　　另一研究主軸是為改善非隔離式700伏特功率元件，因元件之基體效應會導致功率元件效能變差，甚至使積體電路功能失效。利用現有製程技術，不額外增加成本或改變製程參數，只利用佈局技巧設計出一隔離式700伏特功率元件。而此元件在電性結果上，性能是可獲得改善，且優於非隔離式700伏特功率元件。

This thesis is to study the power device of 700V LDMOS in 0.18um technology. It is different from the general 0.5um/1um BCD (Bipolar CMOS DMOS) technology. That is more efficiency and cost savings for integration of low-voltage circuit. To obtain the 700V power component with low Rdson by Synopsys TCAD simulation, layout skills and test results. Finally, achieve the result by fine-tune process.
Another research is to improve the performance of non-isolated 700V LDMOS. The body effect will lead to deterioration and even ineffective in integrated circuit. To design the isolated 700V LDMOS only by layout technology, no additional costs or change process parameters and the performance is improved significantly. The electric characteristic of this isolated device is better than original device.

中文摘要.......................................I
英文摘要......................................II
誌謝.........................................III
目錄..........................................IV
圖目錄........................................VII
表目錄.........................................XI
第一章 緒論.....................................1
1.1 前言.......................................1
1.2 研究動機....................................2
1.3 論文綱要....................................5
第二章 超高壓元件研究與理論.......................6
2.1 高壓元件的應用..............................6
2.2 高壓元件架構................................12
2.3 高壓元件特性................................13
2.3.1 崩潰機制.................................14
2.3.2 接面曲率.................................16
2.4 改善接面耐壓................................18
2.5 RESURF理論.................................19
第三章 超高壓元件研究內容與方法....................23
3.1 前言.......................................23
3.2 基底.......................................23
3.3 淺溝槽隔離..................................25
3.4 內介電層....................................26
3.5 700V LDMOS元件改善..........................32
3.5.1 P型場環...................................32
3.5.2 漂移區與場板...............................36
3.5.3 佈局考量..................................39
3.5.4 接面曲率..................................44
3.6 表面離子電荷.................................47
第四章 隔離式超高壓LDMOS元件設計與結果..............48
4.1 前言........................................48
4.2 元件設計.....................................49
4.3 製作流程.....................................53
4.4 量測結果.....................................60
4.5 元件比較.....................................70
4.6 結論........................................76
第五章 結論......................................77
參考文獻.........................................79

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