臺灣博碩士論文加值系統

本論文探討晶片中靜電放電防護電路的設計及全晶片的靜電放電防護的設計方法並
利用電腦輔助積體電路佈局軟體將防護電路實現於國科會晶片中心教育性晶片的製作。
晶片中靜電放電的防護能力因為薄氧化層，短通道，淺汲極 / 源極接面，低摻雜
汲極，金屬矽化物和多晶金屬矽化物的使用而大幅下降。因此我們改良先前的防護電路並
提出全新的防護電路來克服積體電路中靜電放電防護能力嚴重退化的情形。
在這些電路中，我們利用閘流體當作主要的電路元件因為它的高電流傳導能力和低
箝制電壓並且實驗證明這些防護電路都有非常好的靜電放電防護能力。此外，我們發展出
全新的電路技巧可達到可調式的觸發電壓。所以我們可以有效的控制防護元件的特性並強
化積體電路的防護能力而解決這個嚴重的問題。

In this thesis, comprehensive studies on Electrostatic Discharge
protection circuit design and whole-chip ESD protection methodology have been
made. Several novel ESD protection devices have been proposed. These circuits
were designed by computer-aided IC layout software and fabricated through NSC.
ESD protection ability in IC chip degraded due to the thinner gate
oxide, shorter channel length, shallower drain/source junction, lightly-doped
drain structure, polycide and silicided diffusion. We improve recent published
ESD protection devices and propose new whole protection circuits to enhance
the ESD robustness in modern IC chip.
In these CKT designs, we used an SCR structure as main circuit element
because of its high current conducting ability and low holding voltage. The
excellent ESD protection capability of the circuits was also verified by
experimental data. Besides, we developed novel ESD protection circuit with
designable trigger voltage. With these circuits, we can effectively controll
the caracteristics of ESD protection device with high ESD robustness to solve
the serious ESD stress problem in VLSI/ULSI.
1.1 Introduction
2 ESD phenomena in CMOS VLSI and whole-chip ESD protection circuit design methodology
2.1 Introduction
2.2 Whole-chip ESD protection testing models
2.3 Whole-chip ESD protection
3 Modified-LVTSCR Circuit with CDL theory and LVDTSCR device for ESD protection in CMOS VLSI Technology
3.1 Introduction
3.2 Circuit Configuration
3.3 Device structure
3.4 Circuit Operating Principle
3.5 Experimental Results
3.6 Conclusion
4 Gate-Coupled LVTSCR circuit and DCTSCR device for on-chip CMOS VLSI ESD protection
4.1 Introduction
4.2 Circuit Configuration
4.3 Device structure
4.4 Circuit Operating Principle
4.5 Experimental Results
4.6 Conclusion
5 Conclusion
5.1 Conclusion

[1] Ajith Amerasekera and Charvaka Duvvury,
ESD in Silicon Integrated Circuits, John Wiley \& Sons, 1995.
[2] Ming-Dou Ker and Tain-shun Wu,
CCL Technical Journal, 9.5.1995.
[3] C. Duvvury and R.N. Rountree, "Internal chip ESD phenomena beyond the
protection circuit," IEEE Trans. Electron Device, Vol.35, pp2133-2139, DEC. 1988.
[4] M. D. Jaffe, P. E. Cottrell,
"Electrostatic discharge protection in a 4-bit DRAM,"
EOS/ESD Symp.Proc., Vol. EOS-12, pp. 218-223, 1990.
[5] C. C. Johnson, T. J. Maloney, and S. Qawami,
"Two unusual HBM ESD failure mechanisum on a mature CMOS process,"
EOS/ESD Symp.Proc., Vol. EOS-15, pp. 225-231, 1993.
[6] M. Kelly,
"A comparison of electrostatic discharge model and failure signatures for
CMOS IC's,"
EOS/ESD Symp.Proc., Vol. EOS-17, pp. 175-185, 1995.
[7] Ming-Dou Ker, Hun-Hsien Chang, and Chung-Yu Wu,
"A gate-coupled PTLSCR/NTLSCR ESD protection circuit for
deep-submicron low-vlotage CMOS IC's,"
IEEE JSSC, pp. 38-51, 1997.
[8] Ming-Dou Ker, Hun-Hsien Chang, and Chung-Yu Wu,
"Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI,"
IEEE Trans. Electron Device, pp. 588-598, 1996.
[9] Ming-Dou Ker,
"Whole-chip ESD protection design with efficient VDD to VSS ESD
clamp circuit for submicron CMOS VLSI,"
IEEE Trans. Electron Device, pp. 173-183, 1999.
[10] "EOS/ESD standard for ESD sensitivity testing,"
EOS/ESD Association. Inc. New York}, 1993.
[11] A. Amerasekera and C. Duvvury,
"The impact of technology scaling on ESD robusteness and protection circuit design,"
EOS/ESD Symp., Vol. EOS-16, pp. 237-245, 1994.
[12] A. Chatterjee and T. Polgreen,
"A loe-voltage triggering SCR for on-chip ESD protection at output and input pads,"
IEEE Electron Device Lett, Vol. 12, pp. 21-22, 1991.
[13] Kaoru Narita and Yoko Horiguchi,
"A novel on-chip ESD protection with common discharge line for high-speed CMOS LSI's,"
IEEE Trans. Electron Device}, Vol. 44, pp. 1124-1130, 1997.
[14] Rafael Fried, Yaron Blecher and Shimon Friedman,
"Structure for ESD protection in CMOS processes,"
Microelectron Reliab., Vol. 37, pp. 1111-1120, 1997.
[15] Warren R. Anderson,
"Circuit and process design considerations for ESD protection in advanced CMOS processes,"
Microelectron Reliab., Vol. 37, pp. 1087-1103, 1997.
[16] C. Duvvury and A. Amerasekera,
"ESD: A pervasive reliability concern for IC technology,"
Proc. IEEE, Vol. 81, pp. 690-702, 1993.
[17] Ming-Dou Ker and Hun-Hsien Chang,
"How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggerd on,"
EOS/ESD Symp., 1998.
[18] T. L. Polgreen and A. Chatterjee,
"Improving the ESD failure threshold of silicided NMOS output transistor by ensuring current flow,"
IEEE Trans. Electron Device, Vol. 39, No. 2, pp. 379-388, 1992.
[19] C. Duvvury, C. Diaz, and T. Haddock,
"Achieving uniform NMOS device power distribution for submicron ESD reliabilitys,"
IEDM Tech.Dig, pp. 131-134, 1992.
[20] C. Duvvury and C. Diaz,
"Dynamic gate coulping of NMOS for efficient output ESD protection,"
in Proc. IRPS, pp. 141-150, 1992.
[21] S. Ramaswamy, C duvvury and S. -M. Kang,
"EOS/ESD reliability of deep sub-micron NMOS protection devices,"
in Proc. IRPS}, pp. 284-291, 1995.