臺灣博碩士論文加值系統

本論文以Sigma-Delta Modulation為基礎設計D類音頻放大器。相較於類比式的A類、B類、AB類放大器，D類放大器有高效率、體積小、容易設計等優勢。有別於傳統D類放大器所使用的全橋式功率級，本論文所採用的共用開關之功率級架構，更可節省D類放大器的體積與成本。常見的D類放大器會以Pulse-Width Modulator或是Sigma-Delta Modulator來產生開關切換訊號。Pulse-Width Modulator架構簡單，然而固定的切換頻率使其有倍頻雜訊的問題。Sigma-Delta Modulator架構雖然較為複雜，但沒有倍頻雜訊的問題，並且在開關切換次數上也比Pulse-Width Modulator來得少，因此能獲得更高的效率。本論文將於FPGA實現穩定的Sigma-Delta Modulator DAC，並配合德州儀器的 介面IC 與共用開關之功率級，實現一D類音頻放大器。

This thesis aims at designing Class-D Amplifiers based on the method of Sigma-Delta Modulation. In contrast to Class-A, Class-B, and Class-AB Amplifiers, which use analog designs for circuits, Class-D Amplifiers have the advantages of being highly efficient, smaller in size, and simple to design. Unlike the Full-Bridge Power Stage often found in traditional Class-D Amplifiers, the application of Shared Switch Architecture Power Stage adopted in this thesis helps minimize the size of Class-D Amplifiers while reducing the producing costs. Common Class-D Amplifiers use either the Pulse-Width Modulator or the Sigma-Delta Modulator to generate switching command. The structure of the Pulse-Width Modulator is quite simple, but the fixed switching frequency causes the problem of harmonic distortion. Although the Sigma-Delta Modulator is more complex when it comes to structure, it does not have the problem of harmonic distortion, and compared to the Pulse-Width Modulator, it requires fewer times on the switching process, therefore making it possible to secure higher efficiency. This thesis aims to accomplish the designing and making of a Class-D Amplifier that not only ensures the stability of the Sigma-Delta Modulator DAC employed in FPGAs, but also features the utilization of the Texas Instruments Interface IC and Shared Switch Architecture.

摘 要 i
ABSTRACT ii
誌謝 iii
目錄 iv
圖列 vi
表列 vi
第一章 緒論 1
1.1 簡介 1
1.2 研究內容與目標 5
1.3 論文貢獻 6
1.4 章節概要 6
第二章 橋式架構D類放大器前級調變原理 7
2.1 PULSE-WIDTH MODULATION (PWM) 7
2.2 MULTI-STEP OPTIMAL CONVERTER (MSOC) 9
2.2.1 MSOC系統架構 9
2.2.2 Nearest Neighbor Vector Quantizer 10
2.2.3 Finite Horizon Constrained Optimization 11
2.2.4 MSOC設計範例與效能評測 17
2.3 SIGMA-DELTA MODULATION(Σ-Δ) 22
2.3.1 Σ-Δ的發展由來 22
2.3.2 超取樣(Oversampling) 25
2.3.3 n階數位Σ-Δ調變器系統化簡 26
2.3.4 雜訊轉移函數(Noise Transfer Function) 28
2.3.5 積分器狀態之穩態表示 29
2.3.6 Σ-Δ調變器之穩定條件 31
2.3.7 Σ-Δ調變器設計範例 35
2.4 各種調變方法的分析與比較 42
第三章 共用開關功率級架構之Σ-Δ調變原理 43
3.1共用開關架構之功率級 43
3.2共用開關功率級的限制 44
3.3 N聲道共用開關架構之Σ-Δ調變器系統方塊圖 48
3.4 N聲道共用開關架構之Σ-Δ調變器的穩定性分析 50
3.5共用開關功率級架構之Σ-Δ設計範例 55
第四章 硬體架構與實現 60
4.1 USB轉IIS介面IC 60
4.2 FPGA實驗平台與實作 63
4.2.1硬體介紹(GFEC Cyclone II Starter Kit) 64
4.2.2 FPGA實作 65
4.3功率級實作 70
4.3.1硬體介紹 70
4.3.2電路介紹 72
第五章 效能量測與比較 74
第六章 結論與心得總結 89
參考文獻 91

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