臺灣博碩士論文加值系統

3C產品的發展使得人們生活更加便利的同時，所有電子產品都盡可能輕薄短小讓消費者便於攜帶與使用，同時內部元件也必須追求高效能、低成本的趨勢使產品更有競爭力。而晶圓尺寸越大，同一片晶圓上可生產出來的晶片就越多，將可以降低生產成本，晶圓直徑不斷增加與厚度薄化，勢必在製造過程中產生殘留應力與翹曲等問題。翹曲的產生主要來源在於各元件間熱膨脹係數的不同所引起，進而導致產品生產良率低落、可靠度不佳。
本研究包含內容有三款晶圓的晶圓級晶片尺寸封裝製程對翹曲的初步探討。吾人將以有限元素分析軟體 ANSYS 進行有限元素模型建立，並分析比對其翹曲量。而三款晶圓分別為兩個八吋及一個十二吋，晶圓中的晶粒尺寸也不同，其中分為兩種晶粒尺寸，分別是單一晶粒尺寸為 6730 um x 7194.8 um，切割道寬度為 80 um，切割道長度為 160 um；以及單一晶粒尺寸為 2560 um x 2520 um，切割道寬度為 160 um，切割道長度為 80 um。其中將針對晶圓製程進行模擬分析，模擬研磨、溝槽蝕刻、薄膜沉積及填充等製程，主要分成五個模型，而為了減少元素與節點數量，並減少電腦運算的時間，固依照結構參數建立四分之一有限元素模型。由於不同製程產生相對應的元件，分析時將使用元素的生與死之指令，以滿足製程中不同元件的完成。並利用次模型法來克服元素大小比例問題。分析完後，將比較不同晶圓尺寸，在相同製程流程下所產生的變形。最後在不同的位置上進行單顆晶粒結構模型分析，並比較相同的尺寸晶粒下八英吋以及十二英吋鋁層與矽層之應力值。
模擬結果顯示，兩個八英吋模型在填充CSM製程前，變形量差異不大，但在填充CSM層後，變形量約為原先的兩倍，由此可觀察CSM層對晶圓變形的影響。針對相同大小的晶粒，鋁層以及矽層的應力狀態比較，應力值差異百分比不超過 7 %。由此可了解八英吋以及十二英吋晶圓在製程所產生的效應。

Electronic Packaging reliability is of great concern to semiconductor and electronic product manufacturers. From the first to the fourth generation computer, the tremendous growth of computers and 3C products, and its significant impact on our lives is the invention of the microprocessor.
Wafer level packaging is an important development trend for IC package design. Warpage problem plays an important role in IC encapsulation processes. A few researchers studied the warpage analyses with temperature changes in particular process in steady of the whole wafer processes. The purpose of this research is to analysis of the wrapage of the CMOS in each manufacture process by finite element method.
In finite element model, there are three models: (a) 8 inch wafer with chip size (6370 m×7194.8 m); (b) 8 inch wafer with chip size (2560 m×2520 m); (c) 12 inch wafer with chip size (2560 m×2520 m). Due to the different processes and the dimension scale of different components, the Ealive and Ekill and the submodel technique are used. From global model to four submodels, the wrapage simulation in wafer level to die level is achived. Finally, the Si layer and Al layer equivalent stresses in die level at different locations, inner, middle and outer, are derived.
According to the results, the wrapage between model A and model B is not consequence with respect to die size. However, the wrapage of model C is two times of that of model A. For 8 inch, the equivalent stress of Si layer at outer is 5.61 % greater than that of at inner and the equivalent stress of Al layer at outer is 3.36 % greater than that of at inner. For 12 inch, the equivalent stress of Si layer at outer is 6.64 % greater than that of at inner and the equivalent stress of Al layer at outer is 1.88 % greater than that of at inner.

目錄
中文摘要.............................................................i
ABSTRACT............................................................ii
致謝................................................................iii
目錄................................................................iv
圖目錄..............................................................vi
表目錄..............................................................viii
第一章 緒論..........................................................1
1-1 前言............................................................1
1-2 CMOS製程介紹....................................................4
1-3 文獻回顧........................................................6
1-4 研究動機與目的...................................................8
1-5 研究方法........................................................9
第二章 有限元素模型..................................................11
2-1 構裝體幾何尺寸...................................................12
2-2 構裝體機械性質...................................................13
2-3 邊界條件........................................................15
2-4 全域模型........................................................16
2-5 次模型一........................................................19
2-6 次模型二........................................................22
2-7 次模型三........................................................25
2-8 次模型四........................................................26
第三章 結果與討論....................................................27
3-1 晶圓全域模型之結果比較............................................27
3-2 晶圓次模型一之結果比較............................................31
3-3 晶圓次模型二之結果比較............................................36
3-4 晶圓次模型四之結果比較............................................43
結論................................................................45
參考文獻............................................................47

[1]Michael Quirk, Julian Serda, “Semiconductor Manufacturing Technology,” Advanced Micro Devices, 2003.
[2]Yuan Lin Tzeng, Nicholas Kao, Eason Chen, Jeng Yuan Lai, Yu Po Wang and C.S. Hsiao, “Warpage and Stress Characteristic Analyses on Package-on-Package (PoP) Structure,” 9th Electronic Packaging Technology Conference, pp. 482~487, 2007.
[3]A. H. Abdelnaby, G.P. Potirniche, F. Barlow1 and A. Elshabini1, “Numerical Simulation of Silicon Wafer Warpage Dueto Thin Film Residual Stresses,” Microelectronics and Electron Devices, pp. 9~12, 2013.
[4]R. B. R. van Silfhout, W. D. van Driel, Y. Liz, G. Q. Zhang and L. J. Emst, “Prediction of back-end process-induced wafer Warpage and experimental verification,” Electronic Components and Technology Conference, pp. 1182~1187, ECTC 2002.
[5]S. Okikawa, M. Sakimoto, M. Tanaka, T. Sato, T. Toya and Y. Hara,” Stress Analysis of Passivation Film Crack for Plastic Molded LSI Caused by Thermal Stresses,” International Symposium Testing and Failure Analysis, pp. 275~280, 1983.
[6]Nishimura, “Life Estimation for IC Plastic Packages under Temperature Cycling Based on Fracture Mechanics,” IEEE Components, Hybrids and Manufacturing Technology, Vol. 12, pp. 637~642, 1987.
[7]鄧上軒, “擴散型晶圓級封裝之翹曲研究,” 國立成功大學, 機械工程學系碩士班, 碩士論文, 2009.
[8]M. R. Ismail, W. J. Basirun and Y. K. Yay, “Analysis on Geometry and Surface of 150 μm Silicon Wafer After Back Grinding and Wet Etching Process,” Solid State Science and Technology, Vol. 16, No 2 , 2008.
[9]Faxing Che, H. Y. Li, Xiaowu Zhang, S. Gao and K. H. Teo, “Wafer Level Warpage Modeling Methodology and Characterization of TSV Wafers,” Electronic Components and Technology Conference, 2011.
[10]C. G. Kessel, S. Gee and J. Murphy, “The Quality of Die Attachment and its Relationship to Stresses and Vertical Die Cracking,” IEEE Components, Hybrids and Manufacturing Technology, Vol. 6, pp.410~420, 1983.
[11]B. Natarajan and B. Bhattacharyya, “Die Surface Stresses in a Molded Plastic Package,” 36th Electronic Component Conference, pp. 540~551, 1986.
[12]Faxing Che, Hongyu Y. Li, Xiaowu Zhang, Shan Gao, and Kenghwa H. Teo, “Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers,” IEEE Transaction on Components, Packaging and Manufacturing Technology, Vol. 2, No. 6, June 2012.
[13]K. Oota and K. Shigeno, “Development of Molding Compound for BGA,” 45th Electronic Components Conference, pp. 78~85, 1995.
[14]G. Kelly, C. Lyden, W. Lawton and J. barrett, “Accurate Prediction of PQFP Warpage,” Electronic Components and Technology Conference, pp. 102~105, 1994.
[15]G. Kelly, C. Lyden, W. Lawton, J. barrett, A. Saboui, H. Page and J. B. Peters, “Importance of Molding Compound Chemical Shrinkage in the Stress an Warpage Analysis of PQFP’s,” IEEE Transactions on Components and Packaging Technologies, Vol. 19, pp. 296~300, 1996.
[16]L. T. Nguyen, “Reactive Flow Simulation in Transfer Molding of IC Packages,” 43rd Electronic Components Conference, pp. 375~390, 1993.
[17]W. B. Young, “Three Dimensional Nonisothermal Mold Filling Simulations in Resin Transfer Molding,” Polymer Composites, Vol. 15, pp. 118~127, 1994.
[18]M. K. Kang, “Simulation of Mold Filling Process during Resin Transfer Molding,” Journal of Material Process and Manufacturing Science, Vol. 3, pp. 297~313, 1995.
[19]C. Loos and G. S. Springer, “Curing of the Epoxy Matrix Composites,” Journal of Composite Materials, Vol. 17, pp. 135~169, 1983.
[20]E. Suhir, “Predicted Residual Bow of Thin Plastic Packages of Integrated Circuit Devices,” ASME Journal of Electronic Packaging, Vol. 114, pp. 467~470, 1992.
[21]E. Suhir and L. T. Manzione, “Predicted Bow of Plastic Packages Due to the Nonuniform Through-Thickness Distribution of Temperature,” ASME Journal of Electronic Packaging, Vol. 114, pp. 329~335, 1992.
[22]M. ST. Jacques, “An Analysis of Thermal Warpage in Injection Molded Flat Parts Due to Unbalanced Cooling,” Polymer Engineering Science, Vol. 22, pp. 241~247, 1982.