臺灣博碩士論文加值系統

本論文提出具粗細偵測延遲時間機制之高解析度之游標尺延遲線(Vernier Delay Line, VDL)量測電路之研究，藉由粗細偵測機制，大幅縮短量測時間以提高操作速度，使得量測電路能在具高解析度偵測下同時擁有快速測得待測物之相關資訊，並能達到每一級皆有穩定的延遲時間，以確保資料的準確性。其電路設計上乃是運用游標卡尺的原理，使得兩訊號分別經過兩個不同延遲時間的累積偵測後，產生細微的延遲時間差，以達到非常高的解析度。

本論文呈現具粗細偵測機制之高解析游標尺延遲線的設計與分析，改善傳統游標尺延遲線電路在高解析度與少延遲級數上無法兼顧的問題；同時也改善量測電路在高解析要求下所需耗費的量測時間。本論文所提之具粗細偵測機制之高解析游標尺延遲線電路中，輸入訊號先經過第一階段的粗偵測游標尺延遲線電路，快速測得待測區間後，再經由控制電路分別將延遲後的兩延遲訊號送至第二階段的細偵測游標尺延遲線獲得更精確的量測結果，最後則由並列輸入串列輸出電路將結果值輸出以便觀察。為驗證論文提出電路的實效性，我們結合游標尺延遲線與亞穩態現象，設計出一具粗細偵測機制之高解析游標尺延遲線之亞穩態量測電路。以D型正反器作為待測電路，量測其亞穩態發生的時間點，模擬於0.18 μm CMOS 1.8V製程下，操作頻率100MHz，僅使用16級延遲單元於細偵測機制上即可達到2.0ps解析度之時間差，量測範圍擴及220ps。相較於使用傳統游標尺延遲線電路，大為節省延遲元件級數與量測時間，同時並將量測電路實現於晶片上，其佈局後之模擬結果也與佈局前達到一致。

This thesis presents a fine and course delay mechanism detects high resolution VDL(Vernier Delay Line, VDL) study of the measurement circuit, with fine course detection mechanism, greatly reducing the measurement time in order to improve the operating speed so that the measurement circuit can detect with high resolution simultaneously measured analyses with fast, related information, and can reach every one stabilization delay time to ensure data accuracy. The circuit design, but the principle of using a vernier caliper, making the two signals through two different delay times, respectively, the cumulative detection, resulting in slight delay time difference, in order to achieve a very high resolution.

This thesis presents a fine course detection mechanisms HD VDL design and analysis, improve the traditional vernier delay line circuit in the high-resolution and low delay progression can not take into account the problems; but also to improve the measurement circuit in the high-request the necessary analytical measurement time consuming. This paper proposed a fine course detection mechanism of the high-resolution vernier delay line circuit, the input signal is first detected after the first phase of coarse vernier delay line circuit, rapid test detected after the interval, and then through the control circuit, respectively, after two delays will delay the second phase of the signal sent to the fine detection VDL obtain more precise measurement results, and finally by the parallel input serial output circuit outputs the resulting value for observation. In order to verify the effectiveness of the circuit thesis, we combine VDL and metastability phenomena, to design a fine course detection mechanism VDL high-resolution measurement of the metastable state circuitry. The D flip-flop circuit as a test, measure the time of occurrence of metastable, the simulation process in 0.18 μm CMOS 1.8V, the operating frequency of 100MHz, the delay unit 16 only the detection mechanism can be in the small the time difference reached 2.0ps resolution, measurement range extended 220ps. Compared with traditional vernier delay line circuit, greatly saving delay element progression and measurement time, and simultaneously measuring circuit on the wafer, the layout of the simulation results are also consistent with the layout of the front reach.

中文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
英文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
一、緒論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 研究目的與應用. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 研究方法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 研究流程. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5 論文架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
二、傳統游標尺延遲線電路原理與應用. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 游標尺延遲線原理. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 游標尺延遲線於抖動量測電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 游標尺延遲線之時間至數位轉換器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 單級游標尺延遲線於時間至數位轉換器. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 兩級游標尺延遲線之時間至數位轉換器. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 一階游標尺延遲線之單斜率類比至數位轉換器. . . . . . . . . . . . . . . . . . . . . . 17
2.7 二階游標尺延遲線之單斜率類比至數位轉換器. . . . . . . . . . . . . . . . . . . . . . 19
三、傳統游標尺延遲線電路分析. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1 串列式延遲線. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2 游標尺延遲線之時間至數位轉換器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 傳統游標尺延遲線電路架構比較. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
四、具粗細偵測機制之高解析游標尺延遲線電路. . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 整體架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1 時序圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.2 系統架構圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.3 規格設計. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2 游標尺延遲元件之設計. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3 待測電路與控制電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.1 待測電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.2 控制電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4 輸出電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
五、新型具粗細調游標尺延遲線電路之實現與實驗設計. . . . . . . . . . . . . . . . . 40
5.1 實驗設計與考量. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2 佈局考量. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.4 效能比較. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.5 量測考量. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
六、結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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