臺灣博碩士論文加值系統

本論文提出一輸出電壓漣波最小化之控制策略，採用脈波寬度調變(Pulse Width Modulation, PWM)結合脈波振幅調變(Pulse Amplitude Modulation, PAM)的控制觀念，將其應用於48V±20%轉12V的直流-直流降壓型轉換器，而此系統架構是使用兩組轉換器串接(Cascaded)而成，其前級架構為一升降壓型轉換器用以調控後級輸出電壓，而其後級架構為兩相交錯式降壓型轉換器用以提供大的輸出電流。理論上，若將後級兩相降壓型轉換器之責任週期操作於0.5並互相延遲半個切換週期且兩相電流於任時皆相等時，則後級轉換器的電流漣波可以完全消除，進而得到無漣波之輸出電壓。但因後級的責任週期固定後，負載變動或輸入電壓變動時將無法穩定於額定的輸出電壓，故外加前級用來調控後級輸入電壓的大小，並迴授後級之輸出電壓至前級控制器用以穩定後級轉換器的輸出電壓，使得轉換器操作在全負載下及可允許的輸入電壓變動範圍內均可穩定於額定的輸出電壓。因此，前級轉換器電壓的調整範圍必須兼具升壓與降壓之功能，故前級採用升降壓型轉換器。然而，因為後級兩相轉換器並非完全對稱，故加入均流控制法，對責任週期進行微調，使得輸出電流能均勻地由兩相提供。於本論文中，首先，藉由IsSpice模擬軟體初步驗證所提架構之可行性；其次，結合AHDL軟體與Matlab/Simulink軟體以模擬及驗證程式撰寫之正確性；最後，採用Altera公司所生產的FPGA晶片EP2C20F484C8以做為整個系統的控制核心來實作驗證本架構之可行性。

In this thesis, minimization of the output voltage ripple is presented based on the pulse width modulation (PWM) along with the pulse amplitude modulation (PAM), and applied to a DC-DC buck converter with the input voltage of 48V±20% and the rated output voltage of 12V. This system is implemented by two converters cascaded. The first-stage converter is a buck-boost converter used to regulate the output voltage of the second stage; the second-stage converter is an interleaved two-phase buck converter used to offer a large output current. In theory, if the duty cycle of the second-stage converter is set to 0.5 and the difference in phase between the two phases is , then the output current ripple is cancelled entirely, and hence the output voltage is ripple-free.
However, if the duty cycle of the second-stage converter is fixed, then the output voltage is changed due to variations in load current or input voltage. Consequently, one additional converter, buck-boost converter, is used as the first-stage converter, which can regulate the output voltage of the second-stage converter to the prescribed value as closely as possible all over the load current and input voltage ranges. Furthermore, in actuality, there exist some differences in circuit parameter between the two phases, and hence current sharing is required so as to make the load current extracted from two phases as evenly as possible by finely adjusting duty cycles. In this thesis, the proposed control strategy is firstly simulated by IsSpice, secondly the corresponding program is verified by AHDL cooperated with Matlab/Simulink, and finally one field programmable gate array (FPGA) chip, named EP2C20F484C8 and made by Altera, is used as a control kernel of the system, so as to demonstrate the feasibility of the proposed control scheme.

目 錄

中文摘要 i
英文摘要 iii
誌謝 v
目錄 vi
表目錄 x
圖目錄 xii
第一章 緒論 1
1.1 研究背景與動機 1
1.2 研究方法 9
1.3 論文架構 10
第二章 兩級轉換器原理介紹 11
2.1 升降壓型轉換器簡介 11
2.1.1 升降壓型轉換器連續導通模式之穩態分析 12
2.1.2 升降壓型轉換器CCM/DCM邊界條件 19
2.2 降壓型轉換器簡介 20
2.2.1 降壓型轉換器連續導通模式之穩態分析 21
2.2.2 降壓型轉換器CCM/DCM邊界條件 28
第三章 所提輸出電壓漣波最小化之方法 30
3.1 輸出電壓漣波最小化之觀念 30
3.2 所提之均流技術 41
3.2.1 均流技術介紹 41
3.2.2 平均電流法 42
3.2.3 直接主僕法 44
3.2.4 自動主僕法 45
3.2.5 本文之均流技術 47
3.2.5.1 取樣方式 47
3.2.5.2 均流控制方式 49
3.3 介紹脈波振幅調變及脈波寬度調變之觀念 50
第四章 硬體電路設計 55
4.1 系統架構 55
4.2 系統之研製 57
4.2.1 閘極驅動電路 57
4.2.2 前級升壓型轉換器 59
4.2.2.1 電感之設計 60
4.2.2.2 輸入電容設計 66
4.2.2.3 功率開關元件之選配 67
4.2.2.4 二極體元件之選配 70
4.2.2.5 輸出電容之設計 72
4.2.3 後級交錯式降壓型轉換器 73
4.2.3.1 電感之設計 74
4.2.3.2 功率開關元件之選配 76
4.2.3.3 二極體元件之選配 77
4.2.3.4 輸出電容之設計 78
4.3 感測電路之設計 79
4.3.1 直流輸出電壓感測器 79
4.3.2 電流感測器 82
4.3.3 類比數位轉換器 87
第五章 全數位化控制器之設計 92
5.1 前言 92
5.2 控制器簡介 93
5.2.1 類比控制 93
5.2.2 數位控制 93
5.2.3 數位控制器與類比控制器之比較 95
5.3 古典PID控制器 96
5.4 程式流程及規劃 99
5.4.1 前級穩壓控制之程式流程 99
5.4.1.1 模組 101
5.4.1.2 通訊介面之 模組程式撰寫 101
5.4.1.3 穩壓迴路之 運算模組程式撰寫 104
5.4.1.4 穩壓迴路之 模組程式撰寫 109
5.4.2 後級均流控制之程式流程 111
5.4.2.1 均流迴路之 運算模組程式撰寫 113
5.4.2.2 均流迴路之交錯式 模組程式撰寫 116
第六章 系統模擬與實驗結果之探討 120
6.1 電路模擬之結果 120
6.1.1 模擬波形 120
6.1.2 之模擬波形 130
6.2實測之結果 133
6.2.1 額定輸入電壓下之相關波形圖 133
6.2.1.1 負載10%(0.84A) 133
6.2.1.2 負載50%(4.2A) 138
6.2.1.3 負載100%(0.84A) 143
6.2.2 額定輸入電壓+20%下之相關波形圖 148
6.2.2.1 負載10%(0.84A) 148
6.2.2.2 負載50%(4.2A) 153
6.2.2.3 負載10%(8.4A) 158
6.2.3 額定輸入電壓-20%下之相關波形圖 163
6.2.3.1 負載10%(0.84A) 163
6.2.3.2 負載50%(4.2A) 168
6.2.3.3 負載100%(8.4A) 173
6.3 結論 178
6.4 後級兩相電路之均流暫態波形 179
6.4.1 額定輸入電壓時之負載變動的電感電流波形 179
6.4.1.1 負載由25%加載至50%及由50%卸載至25% 179
6.4.1.2 負載由50%加載至75%及由75%卸載至50% 180
6.4.1.3 負載由75%加載至100%及由100%卸載至75% 181
6.4.2 額定輸入電壓+20%時之負載變動的電感電流波形 182
6.4.2.1 負載由25%加載至50%及由50%卸載至25% 182
6.4.2.2 負載由50%加載至75%及由75%卸載至50% 183
6.4.2.3 負載由75%加載至100%及由100%卸載至75% 184
6.4.3 額定輸入電壓-20%時之負載變動的電感電流波形 185
6.4.3.1 負載由25%加載至50%及由50%卸載至25% 185
6.4.3.2 負載由50%加載至75%及由75%卸載至50% 186
6.4.3.3 負載由75%加載至100%及由100%卸載至75% 187
第七章 結論與未來展望 191
7.1 結論 191
7.2 未來展望 191
參考文獻 193
符號對照表 205

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