臺灣博碩士論文加值系統

本研究是以近三年“銅導線晶片熱音波銲線製程研究”的結果為基礎，將銅導線晶片之熱音波銲金線技術(Thermosonic gold wire bonding)進一步轉化提昇至覆晶接合技術的層次。首先在第一階段開發熱音波銲線製程在銅導線晶片的銲墊(Bond pads)進行金球凸塊陣列(Placing Au/Cu ball stud bumps array on bond pads)，此技術與銲線(Wire bonding)最大不同在於植凸塊的製程係於銲墊銲著球形銲點後，即將金線扯斷而成覆晶用之凸塊(stud bump)。接著以覆晶接合(Flip chip bonding)技術將已整平之凸塊陣列以熱音波銲著在銅銲墊陣列陶瓷基板上，完成晶片上板(Chip on board, COB)之封裝接合製程。
在研究方法上主要為製程開發、物性測試，其中製程開發含括接合技術與凸塊式覆晶接合技術之研究，而為配合高訊號傳輸速度要求之銅導線晶片，凸塊材料選擇常用之金凸塊，因銅金屬銲墊在大氣環境進行熱音波製程常伴隨氧化膜問題，所以需有特殊製程防止銅墊氧化。
經由實驗開發凸塊式覆晶製程，期使解決銅導線晶片後段之接合問題，同時徹底了解銅銲墊凸塊式覆晶接合機理及最佳條件。

Flip chip assembly is an attractive solution for high performance and miniaturized microelectronics packaging. A well-established process for flip chip assembly is based on lead-tin solder, which requires flux to remove oxide during assembly. While it serves high yield and reliable connections, soldering requires complex process and sometimes involves materials hazard to the environment. Alternatives such as lead-free assembly processes have been the focus of many researches and developments in recent years. These fluxless techniques include pressure contacts or thermocompression bonding enhanced by conductive adhesives, thermosonic bonding and bonding by fusible metals.
In this research, thermosonic bonding technique is adopted to form bumps. Bumps forming procedure is a mechanical-single point bumping technology derived from the conventional thermosonic wire bonding process. Deviations in the height of bump with remaining tail are observed using Au wire. Hence, the bumps should be leveled to obtain a planar bumps array by a flat tool prior to subsequent Flip Chip thermosonic bonding.
The research approach is, first, to develop a process for thermosonic gold stud bump bonding (SBB) on copper pads using design of experiment (DOE). In order to enhance the bonding strength we first deposited a silver film as a bonding layer due to very good atomic inter-diffusion between silver and gold. In addition, silver layer also prevents copper pad from oxidizing so as to improve bondability. To optimize parameters for stud bump bonding process, we discuss the influence of ultrasonic power and temperature on bonding strength.
Then we use the same deposition profile on the Al2O3 ceramic substrate to investigate the feasibility of thermosonic flip chip die bonding process. Also, we discuss the influence of ultrasonic power and bonding load on shear strength between flipped bonded dies and substrates.

Table of contents

Abstract………………………………………………………………………………………………………………ⅠTable of contents………………………………………………………………………………………….…..Ⅲ
List of Figures…………………………………………………………………………………………………..Ⅴ
List of Tables…………………………………………………………………………………………………….Ⅷ

Chapter 1. Motivation and goals……….……………………..…..………………………….…………...1
1.1 Infrastructure…...………………………………………………………………...…………....…1
1.2 Chips with copper interconnects………...………………………………………..……2
1.3 Stud bump bonding for flip chip process…………………………..………………4
1.4 Bump leveling……………………………………………………………..…………………….5
1.5 Flip Chip……………………………………………………………………………………..……..6
1.6 The limitations of flip chip process……………………………………..…………….7
1.7 Objectives…………………………………………………………………………….……………8


Chapter 2. Background of technology…………………………………………………....................11
2.1 Thermosonic wire bonding…............................................................................................11
2.2 Chips with copper interconnects…………………………………………….………..13
2.3 Flip chip...........................................................................................................................................21


Chapter 3. Literature review…………………………………………………………………………….....28
3.1 Thermosonic wire bonding process for chips with copper pads……..28
3.2 The effects of silver bonding layer on gold wire thermosonic bonding……………………………………………………………………………..…………..…30
3.3 Stud bump bonding………………………………………………..……………...…………31
3.4 Reilability………………………………………………………….………………………...…...32
3.5 Oxidation of copper pads…………………………………………………………....……33
3.6 Influence of intermetallic compounds……………………………………....…..….34
3.7 Thermal stress……………………………………………………………..…………………....34


Chapter 4. Specimen preparation and experimental procedure….…………...….39
4.1 Chips with copper pads………….…………………………………………………..……39
4.2 Stud bump bonding………………………………………………………………………....41
4.3 Flip chip bonding…………………………………………………...…………….....……….43
4.4 Flow chart………………………………………………………………………………..………45


Chapter 5. Results and discussions…………...…………………………………..…………………...46
5.1 Bonding strength of Au bumps………….. ………….. ………….. ………….. ……..46
5.2 Compositional analysis……….. ………….. ……….. ………….. ……….. ………….. ..62
5.3 Roughness of Ag surface under different temperature……….. …………..71
5.4 Bonding strength of bonded flip chip……….. ………….. ……….. ………….. ... 76

Chapter 6. Conclusions and future works…………………………………………….……….…92
6.1 Conclusions…………………………………………………………………………...………...92
6.2 Future works…………………………………………………………………...……………….93

References ………………………………………………………………………………………………………………94

Chapter 1
[1.1]盧思維, 新世代IC構裝之趨勢與機會研討會精要.- 摘自PRISMARK, 覆晶及銅晶片構裝聯盟季刊, No. 4, 89年12月31日, pp. 5-16.
[1.2]J. Ida, M. Yoshimaru, T. Usami, A. Ohtomo, K. Shimokawa, A. Kita, M. Ino, Proceedings of VLSI Technology Symposium (1994), pp.59-60.
[1.3]M. Miyamoto, T. Takwda and T. Furusawa, IEEE Trans. Electron Devices,44, 250(1997).
[1.4]B. Zhao, D. Feiler, V. Ramanathan, Q. Z. Lin, IEEE symposium of VLSI technology digest, 28 (1998).
[1.5]C. K. Hu, J. M. E. Harper, IEEE international symposium on VLSI technology, system, and applications. 18 (1997).
[1.6]C. K. Hu, Material Chemistry and Physics, 52, 5(1998).
[1.7]C. Jin, S. Lin, J. T. Wetzel, Journal of electronic materials, 30, 284 (2001).
[1.8]Y.R. Jeng , J.N. Aoh, C. M. Wang, J. Phys. D: Apply Phys, 34, 3515(2001).
[1.9]E. D. Perfecto, A. P. Giri, R. R. Shields, IBM J. RES. DEVELOP, 42, 597(1998).
[1.10]Chen-Li Chuang, Study on the Thermosonic Wire Bonding Process and Bonding Mechanism for Chips with Copper Interconnects, 國立中正大學機械工程研究所博士論文, 指導教授 敖仲寧, 民國92年
[1.11]J. G. Strandjord, S. Popelar, C. Jauernig, Interconnecting to Aluminum and Copper– Based Semiconductors, Microelectronics Reliability, 42, 265 (2002).

[1.12]L.K Cheah, Y.M. Tan, J. Wei and C.K. Wong, Gold to Gold Thermosonic Flip-Chip Bonding, http://www.flipchips.com
[1.13]Kuo-Ming Chen 1, Kuo-Ning Chiang, Impact of probing procedure on flip chip reliability, Microelectronics Reliability, 43, 2003, pp.123–130.
[1.14]G.Deltoro, N.Sharif, Copper interconnect: migration or bust, Internal electronic manufacturing technology symposium,1999,pp185~187
[1.15]R. R. Tummala, Fundamentals of Microsystems Packaging, in Ch9, McGraw-Hill.
[1.16]Taylor Lyman, William E. Boyer, Metallography, Structures and Phase Diagrams, Vol 8,1973.


Chapter 2
[2.1]J. M. Peterson, IRE Intern. Conv. Record, 10, 3 (1962).
[2.2]K. C. Joshi, Welding J., 50, 840 (1971).
[2.3]G. G. Harman, Wire Bonding in Microelectronics (New York, McGraw-Hill, 1997), p29.
[2.4]林政男, 由界面現象探討電子構裝之熱音波銲線製程, 國立中正大學機械工程研究所碩士論文, 88年6月
[2.5]D. P. Seraphim, R. C. Lasky, C. Y. Li, Principles of electronic packaging, McGraw-Hill, 1993, p 72.
[2.6]H. Treichel, G. Ruhl, P. Ansmann, R. wurl, C.H. Muller, M. Dietlmeier, and G. Maier, DUMIC Conference, 201(1998).
[2.7]D. Edelstein, Proc. IEEE IEDM, 773997).
[2.8]S. Venkatesan, Proc. IEEE IEDM, 769(1997).
[2.9]K. Lau, VMIC Conference, 92(1996).
[2.10]C. Case, A. Komblit, and J. Sapjeta, VMIC Conference, 63(1996).
[2.11]B. Auman, Mat. Res. Soc. Symp. Proc., 337, 705(1994).
[2.12]N. Vrits, K. Heap, W. Burgoyne, and L. Robeson, Mat. Res. Soc. Symp. Proc., 443, 171(1997).
[2.13]P. Townsend, Mat. Res. Soc. Symp. Proc., 476, 9(1997).
[2.14]N. Hendricks, Mat. Res. Soc. Symp. Proc., 443, 3(1997).
[2.15]Semiconductor Industry Association, The National Technology Roadmap for Semiconductor (1997).
[2.16]P. Singer, Semiconductor International, June 1998, p90.
[2.17]G.R. Yang, S. Dabral, X.M. Wu, T. M. Lu, and J.F. McDonald, J. Vac. Sci. Technol., A10(4), 916(1992).
[2.18]Y. Huang, T.R. Yew, W. Lur, and S.W. Sun, VMIC Conference,33(1998).
[2.19]H. Ono, T. Nakano, and T. OHta, Appl. Phys Lett., 64(12), 1511(1994).
[2.20]T. Oku, E. Kawakarni, M. Uekubo, K. Takahiro, S. Yamaguchi, and M. Murakarni, Appled Surface Science,99, 265(1996).
[2.21]K. Holloway, P.M. Fryer, C. Cabral and K.H. Kelleher, J. Appl. Phys., 71(11), 5433(1992).
[2.22]Website: Flip Chip Technologies
[2.23]www.unitive.com
[2.24]Tummala, Fundamentals of Microsystems Packaging, 2002


Chapter 3
[3.1]L. Levine and C. A. Enman, Wire Bonding Strategies to Meet Thin Packaging Requirements-Part 2, Solid State Technology, Jul. 1993, pp.103-107
[3.2]S. Hymes, S. P. Murarka, Passivation of Copper by Silicide Formation in Dilute Siliane, Journal of Applied Physics, 1992, pp. 4623-4625
[3.3]J. N. Aoh, C. L. Chuang and R. F. Ding “On the Oxidation Behavior of Sputtered Copper Film on Si Wafer,” Journal of Material Science and engineering, CSMS, Vol. 34, No.1,2002
[3.4]J.N. Aoh, C.L. Chuang and R.F. Din, Quality Degraded on Au/Cu Ball Bonds by Copper Oxide Formation on Surface of Copper Pad during Thermosonic Wire Bonding Process, submitted to Microelectronics Reliability.
[3.5]Jian Li, J.W. Mager, “Oxidation and Protection in Copper and Copper Alloy Thin Films”, Journal of Applied Physics, 1991, pp. 2820~2827
[3.6]Tu Anh Tran, Lois Yang, Bill Williams, Scott Chen, Audi Chen, ”Fine Pitch and Wire-bonding and Reliability of Aluminum Capped Copper Bond Pad”, Electronic Components and Technology Conference, 2000, pp1674~1680.
[3.7]V. Koeninger, H. H. Uchida, E. Fromm, “Degradation of gold-aluminum ball bonds by aging and contamination”. Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on, v. 18 , n 4 , Dec. 1995, pp. 835-841.
[3.8]T. A. Tran, L. Yong. S. Chen and A. Chen, IEEE electronic Components and Technology Conference, 2000, pp. 1674-1680.
[3.9]J. F. Rohan, G. O’Riordan and J. Boardman, Applied Surface Science, Vol.185, 2002, pp. 289.
[3.10]R. W. Johson, R. Cote, Proceeding of the 1980 International Microelectronics Symposium, 313 (1980).
[3.11]K. James, IEEE Transactions on Parts, Hybrids, and Packaging, 13, 4(1997).
[3.12]P. K. Footner, B. P. Richards, R. B. Yates, Quality and Reliability Int., 3, 177(1987).
[3.13]http//www.smtinline.com/index-en.html
[3.14]http//www.flip-chip.com/photos/arraybump6
[3.15]Bump Bonding Premium Process Software, Kulicke and Soffa Industries, Inc. May 7, 1998
[3.16]Jörg Jasper, Gold or Solder Chip Bumping, the choice is application dependent, EM MICROELECTRONIC-MARIN SA.
[3.17]L. K. Cheah, Y. M. Tan, J. Wei and C. K. Wong, Gold to Gold Thermosonic Flip-Chip Bonding, http//www.flipchips.com/apnotes/CheahArt.pdf.
[3.18]L. Levine, “Ball bumping and coining operations for TAB and flip chip”, International Symposium on Advanced Packaging Meterials, 1997, pp. 110-112.
[3.19]M. Kleina,, H. Oppermannb, R. Kalickib, R. Aschenbrennerb, H. Reichlb, Single chip bumping and reliability for flip chip processes, Microelectronics Reliability, Vol. 39, 1999, pp.1389~1397.
[3.20]Nave J, et al. Flip chip attachment of silicon and GaAs devices on ceramic, silicon and organic substrates using thermocompression bonding. In: Proc. ITAP'96, Sunnyvale, CA. 1996. pp.90-98.
[3.21]Aschenbrenner R, et al. Flip chip attachment using non-conductive adhesives and gold ball bumps, Int Journal of Microcircuits and Electronic Packaging,Vol.18, 1995, pp.154-161.
[3.22]Taylor Lyman, William E. Boyer, Metallography, Structures and Phase Diagrams, Vol 8,1973.
[3.23]P. Schealler, P. Groning, A. Schneuwly, P. Boschung, E. Muller, M. Blanc and L. Schlapbach, Ultrasonic, Vol. 38, 2000, pp212-218.
[3.24]J.N. Aoh, C.L. Chuang, Thermosonic Bonding of Gold Wire onto Copper pad with Titanium Thin Film Deposition, paper to be appeared in Journal of Electronic Materials,2004
[3.25]G.G. Harman, Wire Bonding in Microelectronics (New York, McGraw-Hill, 1997), p29.
[3.26]J. N. Aoh, C. L. Chuang and R. F. Ding “On the Oxidation Behavior of Sputtered Copper Film on Si Wafer,” Journal of Material Science and engineering, CSMS, Vol. 34, No.1,2002
[3.27]J.N. Aoh, C.L. Chuang and R.F. Din, Quality Degraded on Au/Cu Ball Bonds by Copper Oxide Formation on Surface of Copper Pad during Thermosonic Wire Bonding Process, submitted to Microelectronics Reliability.
[3.28]Jian Li, J.W. Mager, “Oxidation and Protection in Copper and Copper Alloy Thin Films”, Journal of Applied Physics, 1991, pp. 2820~2827
[3.29]J.N. Aoh, C.L. Chuang, Thermosonic Bonding of Gold Wire onto Copper pad with Titanium Thin Film Deposition, paper to be appeared in Journal of Electronic Materials,2004
[3.30]J.N. Aoh, C.L. Chuang, Improvement of Bondability of Thermosonic Gold Wire bonding on Copper Pads through Argon Shielding, paper was to be appear in Journal of Electronic Materials, 2004
[3.31]JEDEC (EIA) Solid State Technology Product Engineering Council (Arlington, 1998).
[3.32]Robert E. Reed-Hill, ”Physical Metallurgy Principle”, third edition, 1991, pp.364.
[3.33]Taylor Lyman, William E. Boyer, Metallography, Structures and Phase Diagrams, Vol 8,1973.
[3.34]G.G. Harman, Wire Bonding in Microelectronics (New York, McGraw-Hill, 1997), p29.
[3.35]MIL STD 833C, meth, 1015. 1989.
[3.36]Bharat Bhushan, Chetan Dandavate, Thin-film friction and adhesion studies using atomic force microscopy, J. Appl. Phys.Vol. 87, 2000, pp.1201


Chapter 4
[4.1]EIA/JEDEC STANDARD, Wire Bond Shear Test, EIA/JESD22-B116, Electronic Industrieas Alliance, Arlington, VA, 1998.


Chapter 5
[5.1] EIA/JEDEC STANDARD, Wire Bond Shear Test, EIA/JESD22-B116, Electronic Industrieas Alliance, Arlington, VA, 1998.