臺灣博碩士論文加值系統

摘要

在本論文中， 我們研製增強型、 空乏型元件以技術成熟的琥珀酸濕蝕刻溶液。 此蝕刻溶液在室溫下對於GaAs/AlGaAs兩種材料有非常高的蝕刻選擇性。 由於可以精準地控制蕭基層厚度，我們成功的在同一片晶片上製作出增強型、空乏型元件。 當我們使用雙δ雜載子供層時， 會提高電子濃度， 所以可以獲得比較高的增益 (gm=221/191 mA/mm)和閘極工作電壓擺幅(GVS=1.23/0.55) ， 其元件各別為(空乏型/增強型)。另外也由於使用超晶格AlGaAs/GaAs 當做緩衝層，會改善載子在通道的侷限能力，進而提升元件在高溫下的特性和較小的輸出電導值(gd=0.84/0.63 mS/mm) 。而AlGaAs/InGaAs異質結構場效電晶體的高頻、功率也被討論。 其截止頻率為(ft=21.2/12.5 GHz)， 最大震盪頻率為(fmax=30.5/25.5 GHz)。 當元件操作在2.4G頻率下， 元件輸出功率為(Pout=15.3/13.5 dBm)， 功率效益為(P.A.E. =52.7/41.6%)。

另外， 我們成功地在同一晶片上整合增強型空乏型元件應用於反向器邏輯閘上面，當操作在電源1V室溫下， 其雜訊邊限(NMH=0.266V, NML=0.168V)皆有不錯的表現。而當溫度增加至400K其雜訊邊限(NM)也能維持在0.1 V左右。因此適用於低功率消耗電路、高溫數位電路及混波電路應用。

Abstract

In this work, we fabricated enhancement-/depletion-mode by a developed citric etchant. The etchant near room temperature(23℃) possesses a high GaAs/AlGaAs etching selectivity applied to an etched stop surface. Since it is expected that control Schottky thinner more accurate, we have successfully realized the E-mode and D-mode on the same chip. We use double δ-doped carrier supply layer to enhance two-dimensional electron gas (2DEG) concentration and increase the current driver capability. It is desirable to be able to sustain high extrinsic transconductance (gm=221/191 mA/mm) and large voltage swing (GVS=1.23/0.55) for the D-mode (E-mode) device, respectively. We employ an AlGaAs/GaAs superlattice as a barrier layer against impurity contamination to improve the high-temperature performances. This structure provides isolation of the device from carriers thermally generated in the substrate. The experimental results show lower saturation output conductance (gd=0.84/0.63 mS/mm), good saturation and pinch-off characteristics.

The enhancement-mode (E-mode) and depletion-mode (D-mode) device operation on the same chip and their monolithic integration to form a DCFL inverter by using the double δ-doped AlGaAs/InGaAs pseudomorphic high electron-mobility transistors have been successfully fabricated and investigated. Upon the identical layer structure design, the proposed pHEMT demonstrates different operation modes with distinguished static, microwave-frequency (ft=21.2/12.5 GHz and fmax=30.5/25.5 GHz), and output power characteristics (Pout=15.3/13.5 dBm and P.A.E. =52.7/41.6% at 2.4GHz). In addition, the transfer characteristics, power dissipations, and the noise margins (NMH=0.266V, NML=0.168V at VDD = 1V T=300K) of the monolithic DCFL inverter have also been studied. The noise margins are superiorly maintained above 0.1 V as the ambient temperature increases up to 400K. The present devices are promisingly suitable for the low-power-dissipation, high-temperature digital circuit or the mixed-mode circuit applications.

Contents
Abstract (Chinese)
Abstract (English)
Figure Caption
Chapter 1 Introduction 1
Chapter 2 Conventional Pseudomorphic HEMTs 4
2-1 HEMT Layer Design 4
2-1-1 Cap Layer 4
2-1-2 Schottky Layer 4
2-1-3 δ-doped Carrier Supply Layer 5
2-1-4 Spacer Layer 5
2-1-5 Pseudomorphic InGaAs Channel Layer 6
2-1-6 Buffer Layer 6
Chapter 3 Device Growth and Fabrication 8
3-1 Material Growth 8
3-2 The Improvement of Structure and Process 8
3-2-1 Delta-Doping 8
3-2-2 Citric Buffer Etchant 9
3-3 Device Fabrication 9
3-3-1 Sample Orienting 10
3-3-2 Mesa Isolation 10
3-3-3 Source and Drain Ohmic Contact Formation 10
3-3-4 Gate Schottky Contact Formation 11
3-4 Hall Measurement 11
Chapter 4 Experimental results 13
4-1 DC Characteristics at Room Temperature 13
4-1-1 Current-Voltage Characteristics 13
4-1-2 Extrinsic Transconductance and Saturation Current Density 13
4-1-3 Breakdown Voltage Characteristics 14
4-2 Microwave Characteristics at Room Temperature 15
4-2-1 ft and fmax Characteristics 15
4-2-2 Power Characteristics 16
4-4-3 Noise Characteristics 17
4-2-4 Small Signal Parameter Characteristics 18
4-3 Temperature Characteristics 20
4-3-1 Current-Voltage Characteristics 20
4-3-2 Extrinsic Transconductance and Saturation Current Density 20
4-3-3 Breakdown Voltage 21
4-3-4 ft and fmax Characteristics 22
4-4 Monolithic DCFL Integration Application 23
Chapter 5 Conclusion 25
References 26
Figures 31

Reference
[ 1]C. Y. Lee, H. P. Shiao, K. C. Kuo, H. Y. Wu and W. H. Lin, “Mobility and charge density tuning in double-doped enhancement-mode pseudomorphic high-electron-mobility transistors grown by metalorganic chemical vapor deposition,” Jpn, J. Appl. Phys., vol. 44, no. 8, p. 5909, 2005.
[ 2]M. Ogura, K. Matsumoto, T. Wada, T. Yao, N. Hashizume, and Y. Hayashi, “Self-aligned enhancement mode FET with AlGaAs as gate insulator,” J. Vac. Sci. Technol. B , vol. 3, p. 581, 1985.
[ 3]R. Grundbacher, R. Lai, M. Barsky, R. Tsai, and R. Dia, “Enhancement-mode InGaAs/InAlAs/InP high electon mobility transistor with 0.1um gate,” Jpn, J. Appl. Phys., vol. 41, no. 2B, p. 1108, 2002.
[ 4]L. Nishii, M. Nishitsuji, T. Yokoyama, and S. Yamamoto, “High-current and high transconductance self-aligned P+-GaAs junction HFET of complete enhancement-mode operation,” Jpn, J. Appl. Phys., vol. 38, no. 4B, p. 2555, 1999.
[ 5]M. Passlack, J. K. Abrokwah, and R. Lucero, “Experimental observation of velocity overshoot in N-channel AlGaAs/InGaAs/GaAs enhancement mode MODFETs,” IEEE Electron Device Lett., vol. 21, no.11, p.518, 2000.
[ 6]M. Boudrissa, E. Delos, Y. Cordier, D. Theron, and J. C. De Jaeger, “Enhancement mode metamorphic Al0.67In0.33As/Ga0.66In0.34As HEMT on GaAs substrate with high breakdown voltage,” IEEE Electron Device Lett., vol. 21, no. 11, p. 512, 2000.
[ 7]Y. J. Li, W. C. Hsu, Y. W. Chen, and H. M. Shieh“Depletion- and enhancement-mode In0.49Ga0.51P/InGaAs/AlGaAs high-electron-mobility transistors with high-breakdown voltage, ” J. Vac. Sci. Technol. B, vol. 21, no. 3, p. 981, 2003.
[ 8]C. S. Lin, Y. K. Fang, S. F. Ting, C. C. Wang, H. K. Huang, C. L. Wu, and C. S. Chang, “High performance 12GHz enhancement-mode pseudomorphic HEMT prepared by He plus reactive ion etching,” Solid-State Electronic. vol. 47, p. 695, 2002.
[ 9]H. C. Chiu, S. C. Yang , and Y. J. Chan, “AlGaAs/InGaAs Heterostructure Doped-Channel FET’s Exhibiting Good Electrical Performance at High Temperatures,” IEEE Trans. Electron Devices, vol. 48, no. 10, p.2210, 2001.
[10]Y. J. Li, W. C. Hsu, and S. Y. Wang, “ Temperature-dependent characteristics of an Al0.2Ga0.8As/In0.22Ga0.78As pseudomorphic double heterojunction modulation doped field-effect transistor with a GaAs/AlGaAs superlattice buffer layer,” J. Vac. Sci. Technol. B, vol. 21, no. 2, p. 763, 2003.
[11]H. Tsuji, H. I. Fujishiro, M. Shikata, K. Tanaka and S. Nishi “0.2um gate pseudomorphic inverted HEMT for high speed digital ICs, ” IEEE Trans. Electron Devices, vol. 13, no. 2, p.116, 1996.
[12]H. M. Chuang, S. Y. Cheng, C. Y. Chen, X. D. Liao, R. C. Liu, and W. C. Liu, “Investigation of a new InGaP–InGaAs pseudomorphic double doped-channel heterostructure field-effect transistor (PDDCHFET) ,” IEEE Trans. Electron Devices, vol. 50, no. 8, p.1717, 2003.
[13]S. J. Yu, W. C. Hsu, Y. J. Chen, and C. L. Wu, “High power and high breakdown double-doped In0.35Al0.65As/In0.35Ga0.65As metamorphic HEMT,” Solid-State Electronic, vol. 50, p. 291, 2005.
[14]K. F. Yarn, C. I. Liao, Y. H. Wang, M.P. Houng, and M. C. Chure, “Gate-recessed delta-doping enhancement-mode Al0.2Ga0.8As/In0.15Ga0.85As pHEMTs using a new citric buffer etchant,” Materials Science in Semiconductor Processing, vol. 8, p. 550, 2005.
[15]T. Onuma, A. Tamura, T. Uenoyama, H. Tsujii, K. Nishii, and H. Yagita, “High-transconductance enhancement-mode GaAs MESFET fabrication technology,” IEEE Electron Device Lett., vol. 4, no. 11, p. 409, 1983.
[16]C. S. Cheng, Y. J. Shih, and H. C. Chiu, “A modified angelov model for InGaP/InGaAs enhancement-and depletion-mode pHEMTs using symbolic defined device technolgy,” Solid-State Electronic, vol. 50, p. 254, 2005.
[17]H. C. Chiu, S. C. Yang and Y. J. Chan , “High power density and large voltage swing of enhancement-mode Al0.5Ga0.5As/InGaAs pseudomorphic high electron mobility transistor for 3.5V L-band application,” Jpn, J. Appl. Phys., vol. 41, no. 5A, p. 2902, 2002.
[18]S. Nakajima, K. I. Matsuzaki, K. Otobe, H. Nishizawa, and N. Shiga, “Enhancement-mode GaAs MESFET technology for low consumption power and low noise applications,” IEEE Trans. Microwave Theory Tech., vol. 42, No. 12, p. 2517, 1994.
[19]G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A new method for determining the FET small-signal equivalent circuit,” IEEE Trans. Microwave Theory Tech., vol. 36, no.7, p.1151, 1998.
[20]V. Guru, J. Jogi, M. Gupta, H. P. Vyas, and R. S. Gupta, “An improved intrinsic small-signal equivalent circuit model of delta-doped AlGaAs/InGaAs/GaAs HEMT for microwave frequency applications,” Microwave and Optical Technology Lett., vol. 37, No. 5, p. 376, 2003.
[21]M. Berroth, and R. Bosch, “High-frequency equivalent circuit of GaAs FET’s for large-signal applications,” IEEE Trans. Microwave Theory Tech., vol. 39, no. 2, p. 224, 1991.
[22]H. ROHDIN“Reverse modeling of E/D logic submicrometer MODFET’s and prediction of maximum extrinsic MODFET current gain cutoff frequency, ” IEEE Trans. Electron Devices, vol. 37, no. 4, p.920, 1990.
[23]M. R. Murti, J. Laskar, S. Nuttinck, S. Yoo, A. Raghavan, J. I. Bergman, and P. H. Liu, “Temperature-dependent small-signal and noise parameter measurements and modeling on InP HEMTs,” IEEE Trans. Microwave Theory Tech., vol. 48, no. 12, p. 2579, 2000.
[24]W. C. Liu, K. H. Yu, K. W. Lin, J. H. Tsai, C. Z. Wu, K. P. Lin, and C. H. Yen, “On the InGaP/GaAs/InGaAs camel-like FET for high-breakdown, low-leakage, and high-temperature operations,” IEEE Trans. Electron Devices, vol. 48, no. 8, p.1522, 2001.
[25]W. C. Liu, W. L. Chang, W. S. Lour, S. Y. Cheng, Y. H. Shie, J. Y. Chen, W. C.Wang, and H. J. Pan, “Temperature-dependent investigation of a high-breakdown voltage and low-leakage current Ga0.51In0.49P/In0.15Ga0.85As Pseudomorphic HEMT,” IEEE Trans. Electron Devices, vol. 20, no. 6, p.274, 1999.
[26]M. K. Tsai, S. W. Tan, Y. W. Wu, W. S. Lour, and Y. J. Yang, “Depletion-mode and enhancement-mode InGaP/GaAs delta-HEMT for low supply-voltage applications,” Semicond. Sci. Technol., vol. 17, p.156, 2002.
[27] T. Wang, S. J. Wu, and C. Huang, “Device and circuit simulation of anomalous DX trap effects in DCFL and SCFL HEMT inverters,” IEEE Trans. Comput.-Aided Des.Integr. Circuits Syst, Vol. 12, NO. 11, 1993.
[28]H. Kinoshita, T. Ishida, H. Inomata, M. Akiyama, and K. Kaminishi, “Submicrometer insulated-gate inverted-structure HEMT for high-speed large-logic-swing DCFL gate,” IEEE Trans. Electron Devices, vol. 33, no. 5, p.608, 1986.
[29]S. Kuroda, H. Suehiro, T. Miyata, S. Asai, I. Hanyu, M. Shima, N. Hara, and M. Takikawa, “0.25 pm gate length1 N-InGaP/InGaAs/GaAs HEMT DCFL circuit with lower power dissipation than high-speed Si CMOS Circuits,” IEEE IEDM, p.323, 1992.
[30] I. Adesida, A. Mahajan, and G. Cueva, “Enhancement-mode InP-based HEMT devices and applications,” in Int. Conf. Indium Phosphide and Related Materials, p.493, 1998.
[31]V. K. De, and J. D. Meindl, “Three-region analytical models for MESFET’s in low-voltage digital circuits,” IEEE J. Solid-State Circuits, vol. 26, no. 6, p.850, 1991.