臺灣博碩士論文加值系統

摘 要
本論文中，我們提出了改良型數位座標旋轉計算器（CORDIC）的演算法與硬體架構，並藉著電腦輔助設計軟體實現晶片。與傳統CORDIC不同的是我們藉由一個計算器來取代記憶體，改善了記憶體面積隨輸出位元增加而呈指數成長的問題。再者，因為沒有記憶體的限制，整個系統操作頻率也將被提升。整個演算法已由數學證明，架構亦經硬體實現驗證無誤。因此，改良型的數位座標旋轉計算器將非常適合追求速度與面積的頻率合成器來使用。此設計係經TSMC 0.35 micron 1P4M 製程實現，晶片面積為2.6 x 2.6 mm2。在3.3 V 之電源下，最高時脈速度可達到120 MHz，系統消耗功率為18.5 mW，輸出之正弦與餘弦函數值可達16位元的精確度。
(關鍵字：直接數位頻率合成器、數位座標旋轉計算器、記憶體、鎖相迴路、頻率合成器)

ABSTRACT
In this thesis, we had proposed architecture design and implemented of modified CORDIC algorithm. It is different from conventional CORDIC is that by decomposing an arbitrary rotation angle into a sequence of coarse angles (each of whose tangent value is a power of 2) and a fine angle which is small enough. This architecture can be implemented by performing a sequence of shift-and-add operations in the radix-2 system without any ROM lookup table or real multiplication requirement. It is suitable to be designed in pipeline architecture for performing the high-speed DDFS. This design had fabricated in TSMC 0.35 um 1P4M process. The area of chip is 2.6 x 2.6 mm2. The maximum frequency can be up to 120 MHz at 3.3 V supply voltage.
(Keywords: DDFS, CORDIC, ROM, PLL, Frequency Synthesizer)

Contents
誌 謝 III
Chapter 1 Introduction 1
Background 1
Motivation 3
Objective 4
Thesis Organization 5
Chapter 2 6
Review of Direct Digital Frequency Synthesizer 6
2.1 Sine Wave Generator Based on PLL 7
2.2 ROM-Based Frequency Synthesizer 9
2.2.1 Quadrant Compression Technique 10
2.2.2 Sunderland Architecture 12
2.2.3 Nicholas Architecture 13
2.3 Frequency Synthesizer Based on CORDIC 14
2.3.1 Implementation of Conventional CORDIC Algorithm 14
2.3.2 Redundant Carry-Save Algorithm 16
2.3.3 The Radix-2 Approximating Theorem 17
2.3.4 CORDIC Category 19
Chapter 3 22
Modified CORDIC Algorithm 22
3.1 Similar CORDIC Algorithm 22
3.2 The Derivation of Modified CORDIC Algorithm 24
3.2.1 Coarse and Fine Angle Rotations 24
3.2.2 The Proposed Modified Coarse-Fine Rotation Method 25
3.3 The Approximating Theory of the Fine Angle Term 27
3.4 Example 30
Chapter 4 34
Architecture Design 34
4.1 Accumulator 34
4.2 Modified CORDIC Architecture 37
4.3 The Architecture of the Precomputed Adder 41
4.4 The Structure of Design 42
Chapter 5 46
Chip Implementation and Simulation Results 46
5.1 Chip Implementation 46
5.2 Simulation Results 47
5.3 Performance Comparisons 52
Chapter 6 Conclusion 54
References 55
List of Figures
Figure 1-1 ROM-based DDFS architecture 2
Figure 1-2 CORDIC-based DDFS architecture 3
Figure 2-1 Block diagram of sine wave generator 6
Figure 2-2 Block diagram of PLL 8
Figure 2-3 PLL-based frequency synthesizer 9
Figure 2-4 ROM lookup table 10
Figure 2-5 Sunderland architecture 13
Figure 2-6 Nicholas’ architecture 14
Figure 2-7 The mixed-hybrid CORDIC architecture 20
Figure 2-8 The partitioned-hybrid CORDIC architecture 21
Figure 4-1 Phase accumulator 35
Figure 4-2 Pipeline accumulator 36
Figure 4-3 A 16-bit primitive CORDIC architecture 38
Figure 4-4 The trend of ROM address numbers 39
Figure 4-5 Modified CORDIC architecture 40
Figure 4-6 The architecture of pre-computed fine angle 41
Figure 4-7 The design structure of the datapath 43
Figure 5-1 Gate level simulation 49
Figure 5-2 Post-layout simulation 49
Figure 5-3 Synthesized circuit 50
Figure 5-4 The layout of chip 51
Figure 5-5 The comparison of the hardware 53
List of Tables
Table 2.1 Quadrant mapping table 11
Table 3.1 The approximation of 30
Table 3.2 The 22-bit binary representations of and 32
Table 4.1 The map of output values 45
Table 5.1 Chip characteristic 48
Table 5.2 The size of the ROM lookup table versus the precision 52
Table 5.3 Performance comparisons 53

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