臺灣博碩士論文加值系統

本論文主要是設計一個10 GHz快速鎖定頻率合成器晶片，此頻率合成器僅使用一個電壓控制振盪器來涵蓋9.2GHz至10.4GHz的頻帶範圍，這個電壓控制振盪器採用互補式交叉耦合架構來獲得低相位雜訊的性能，因此晶片面積能夠被大大的減少。在本論文中使用了一組多係數除頻器電路，藉由改變不同的數位輸入碼能改變通道頻率。藉由妥善的設計系統參數，能使鎖定的時間減少，例如電荷幫浦的電流、電壓控制振盪器的增益與迴路頻寬。

在本論文中，鎖定時間能夠低於3.7us。而此頻率合成器使用台積電所提供0.18微米互補式金氧半製程以1.8伏特來完成所有晶片與量測。量測結果顯示頻率鎖定於10GHz時，距離主頻1KHz至100KHz的相位雜訊低於-60 dBc/Hz，而距離主頻1MHz處的相位雜訊為-113.4 dBc/Hz晶片面積包含pad為0.56 mm2。總消耗功率為39mW。

In the thesis, the proposed 10 GHz fast locking frequency synthesizer chip is presented. The proposed frequency synthesizer can cover the frequency range from 9.2 GHz to 10.4 GHz with only using one VCO and the chip area can be greatly reduced. The VCO employs Complementary cross-coupled structure to obtain lower phase noise performance. In this thesis, the multi-modulus divider (MMD) circuit is also used to change the frequency channel by different input digital code. The locking time can be reduced by carefully design system parameters, such as charge pump current, VCO gain and loop bandwidth.

In this thesis, the locking time is lower than 3.7us. The proposed frequency synthesizer is fabricated in a TSMC 0.18-um CMOS process with 1.8 V supply voltage. The measured results show phase noise is lower than -60 dBc/Hz from 1 kHz to 100 kHz offset and -113.4 dBc/Hz at 1 MHz offset with locked in 10GHz. The chip area of the frequency synthesizer is smaller than 0.56 mm2 including the pads. The power consumption is 39mW from a 1.8V supply.

List of Figures III

List of Tables VI

CHAPTER 1 Introduction 1
1.1 Motivation 1
1.2 Focus and Contributions 2
1.3 Organization of This Thesis 2

CHAPTER 2 The PLL-Based Frequency Synthesizers 5
2.1 Wireless Transceiver 5
2.2 Phase-Locked Loop 6
2.2.1 Integer-N Frequency Synthesizer 7
2.2.2 Fraction-N Frequency Synthesizer 8
2.3 Figures of Merit of a Frequency Synthesizer 9
2.3.1 Jitter 9
2.3.2 Phase Noise 10
2.3.3 Spurs 11
2.4 Building Blocks of Frequency Synthesizer 11
2.4.1 Phase Frequency Detector (PFD) 11
2.4.2 Charge Pump (CP) 14
2.4.3 Loop Filter 14
2.4.4 Voltage-Controlled Oscillator (VCO) 15
2.4.5 Frequency Divider 16
2.5 Loop Filter Design 16
2.5.1 First-Order Loop Filter 16
2.5.2 Second-Order Loop 18
2.5.3 Third-Order Loop 21
2.6 Frequency Synthesizer Paper Survey 22

CHAPTER 3 Voltage-Controlled Oscillator Circuit Design 25
3.1 Introduction 25
3.2 Oscillator Theory 26
3.3 Ring Oscillator 27
3.4 LC-Tank VCO 28
3.4.1 Resonator Theory 28
3.4.2 LC-Tank Architecture 29
3.5 Passive Components in an LC-Tank VCO 30
3.5.1 Resistance 30
3.5.2 Capacitor 31
3.5.3 Varactor 31
3.5.4 Inductor 33
3.5.5 Transformer 35
3.6 Design and Implementation of LC-Tank VCO 36

CHAPTER 4 10 GHz Frequency Synthesizer Chip Design 43
4.1 Introduction 43
4.2 System Behavior Modeling 44
4.3 Circuits Architecture 47
4.3.1 Phase Frequency Detector (PFD) 47
4.3.2 Charge Pump (CP) 50
4.3.3 Loop Filter 52
4.3.4 Voltage-Controlled Oscillator 56
4.3.5 Frequency Divider 56
4.3.5.1 Source-Coupled Logic 57
4.3.5.2 Differential to Single-Ended Circuit 58
4.3.5.3 TSPC Divider 60
4.3.5.4 Multi-Modulus Divider 61
4.4 Frequency Synthesizer Simulation 66
4.5 Summary 69

CHAPTER 5 Chip Measurement Results 71
5.1 RF Chip Layout Considerations 71
5.2 RF Chip Measurement Considerations 72
5.2.1 Chip Floor Plan and PCB Design 72
5.2.2 Measurement Instrument 74
5.2.3 Test Environment Setup 75
5.3 Measurement Results 77
5.4 Performance Summary and Comparison 79


CHAPTER 6 Conclusions and Future Work 81
6.1 Conclusion 81
6.2 Future Work 81

Reference : All project chip design and Measurements 83
Appendix I : All project chip design and Measurements 87
Appendix II : Publication List and Award 95

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