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研究生:李昱樞
研究生(外文):Yu-Shu Li
論文名稱:應用於降低突波干擾之直流-直流轉換器
論文名稱(外文):Design of DC-DC Converter with spur reduction technique
指導教授:李宇軒李宇軒引用關係
指導教授(外文):Yu-Hsuan Lee
口試委員:陳超群莊基男
口試委員(外文):Chao-Chyun ChenChi-Nan Chuang
口試日期:2018-06-17
學位類別:碩士
校院名稱:元智大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:79
中文關鍵詞:直流/直流降壓轉換器展頻降低突波
外文關鍵詞:DC/DC Buck converterSpread SpectrumSpur Reduction
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本論文提出了一個可以降低突波干擾之直流/直流轉換器。在本論文中,直流/直流轉換器透過展頻的技術應用,設計一上/下數計數器來控制頻率的變化及切換來達到展頻的效果,使得輸出的突波大小能夠有效的降低。
本設計已透過標準的TSMC0.18um的製程進行設計模擬,展頻後的頻段由650KHZ~1.295MHZ,共計有16個頻段,每個頻段頻率間隔為43KHZ,每個頻段切換的頻率為15.25KHZ,在負載電流在50mA到500mA的範圍內皆可提供穩定的輸出電壓1.2V,頻譜最多可降低27dB。
A DC-DC converter with spur reduction technique is presented in this paper. To achieve this goal, we use the spread spectrum technique and design an updowncounter to change the frequency and switching the frequency, so that we can reduce the spur effectively.
A buck converter with spur reduction technique has been simulated in standard TSMC 0.18um process. The result is that, the system switching frequency spread from 650KHZ to 1.295MHZ with a frequency step 43KHZ between 16 switching frequency, and the changing rate is 15.25KHZ. It also can regulate output voltage of 1.2V when load current change from 50mA to 500mA, and maximum magnitude of spur reduction can achieve 27dB.
摘要 II
ABSTRACT III
誌謝 IV
目錄 V
表目錄 VII
圖目錄 VIII
第一章 緒論 1
1.1研究動機 1
1.2研究背景及簡介 2
1.3論文架構簡介 3
第二章 直流/直流穩壓器概論 4
2.1直流/直流穩壓器分類 4
2.2切換式直流/直流轉換器 6
2.2.1降壓型轉換器(Buck Converter) 6
2.2.2升壓型轉換器(Boost Converter) 8
2.2.3升降壓型轉換器(Buck Boost Converter) 11
2.3控制電路模式 13
2.3.1脈衝寬度調變模式(Pulse-Width Modulation) 13
2.3.2脈衝頻率調變模式(Pulse-Frequency Modulation) 15
2.3.3脈衝寬度調變模式及脈衝頻率調變模式比較 16
2.4補償器的分類 17
2.4.1 PI Type補償器 18
2.4.2 PI Type II補償器 20
2.4.3 PI Type III補償器 22
2.5切換式穩壓器各項規格說明 25
2.5.1輸出漣波電壓( Output Voltage Ripple ) 25
2.5.2電源電壓調節率( Line Regulation ) 25
2.5.3負載調節率( Load Regulation ) 25
2.5.4功率損失( Power Loss ) 26
2.5.5轉換效率( Power Efficiency ) 27
第三章應用於降低突波干擾之直流/直流降壓轉換器設計 28
3.1降低突波干擾原理 28
3.2系統架構與規格 29
3.3系統小訊號分析 30
3.3理想系統模擬 33
第四章 系統電路設計與模擬 39
4.1磁滯比較器(Hysteresis Comparator) 39
4.2鋸齒波產生器(Ramp Generator) 43
4.3緩啟動電路( Soft-Start ) 47
4.4 Dead Time Control Circuit 48
4.5 上/下數計數器( Up/Down Counter ) 51
4.6 邏輯控制電路( Logic Control Circuit ) 53
4.7 完整系統模擬 56
4.7.1 系統暫態模擬 56
4.7.2 頻譜圖 66
第五章 晶片佈局 75
5.1量測考量 75
第六章 結論 76
6.1結論 76
6.2文獻比較 77
6.3未來研究與改進 77
參考文獻 78
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