臺灣博碩士論文加值系統

本論文深入與廣泛地研究金氧半場效電晶體與絕緣層上覆矽金氧半場效電晶體之高頻雜訊，其內容涵蓋元件之物理特性與其在電子電路之應用。為此，論文中觸及諸多範疇，如以物理特性為基礎之數值模擬、雜訊之特性、完整之模型與低雜訊放大器之設計方法等。
首先，提出金氧半場效電晶體元件之非區域性通道熱雜訊模型，此模型可以適切描述次微米/深次微米元件操作於三極區與飽和區之通道熱雜訊。其次，探討以物理特性為基礎並可應用在射頻電路之金氧半場效電晶體汲極電流雜訊的精確模型，內容闡明擴散電流與熱雜訊之效應，並提出完整之感應閘極電流雜訊模型。再者，提出以物理特性為基礎之絕緣層上覆矽金氧半場效電晶體之雜訊模型。最後，鑒於熱載子應力對射頻電路之影響，提出應力後之金氧半場效電晶體雜訊模型。
內容所發展的是省時之計算機輔助設計之模型，並深入探討元件之物理特性與高頻雜訊行為。模型之模擬結果與實驗數據相符，由此可以驗證模型之正確性。

This dissertation provides extensive and detailed information about MOSFET and SOI MOSFET noises both in terms of device physics and detailed design guidelines for circuits. To achieve these goals, this dissertation tackles various areas such as physics based numerical simulation, noise characterization, compact modeling, and finally LNA design methodologies.
First, we present a nonlocal thermal channel noise model to describe the thermal noise behavior in the MOSFET devices, it is capable of simulating the channel thermal noise of submicron / deep-submicron MOSFET devices operated in both the triode and saturation regions. Secondly, we propose an accurate physics-based complete drain current MOSFET noise model for RF circuit design, it clarifies the effects of diffusion and thermal noise. A complete induced-gate current noise model is also proposed. Thirdly, we explore the importance of the hot-carrier stress effect on the high-frequency MOSFET device and circuit noises, therefore, a stressed high frequency noise model is developed. The modeled results of fresh and post-stress MOSFET minimum noise figure are compared with the experimental data. Finally, a physical based closed-form model for SOI MOSFETs is derived. Since the downscaling of the feature size, SOI MOSFETs have been considered as a candidate for the applications in the radio frequency (RF) circuit design.
The above models are time-saving CAD models, these results give useful device physics insight into the high-frequency device noise. The accuracy of the models has been verified by experimental data, and reasonable agreements have been obtained.

論文中文摘要 iv
ABSTRACT v
誌謝 vi
TABLE OF CONTENTS vii
LIST OF FIGURES ix
CHAPTER 1 Introduction 1
1.1 Motivation 1
1.2 Overview 3
CHAPTER 2 Fundamentals of Noise 6
2.1 What is Noise 6
2.2 Thermal Noise 7
2.3 Flicker Noise 10
2.4 Shot Noise 12
2.5 Generation-Recombination Noise 13
2.6 Noise Figure 13
CHAPTER 3 A Nonlocal Channel Thermal Noise Model for nMOSFETs 16
3.1 Introduction 16
3.2 Thermal Noise Model 18
3.3 Comparison with Experimental Data and Discussion 20
3.4 Conclusion 24
CHAPTER 4 A Unified Model for High-Frequency Current Noise of MOSFETs 33
4.1 Introduction 33
4.2 Review 34
4.3 Model 38
4.4 Discussion and Results 42
4.5 Conclusion 44
4.6 Appendix 46
CHAPTER 5 Modeling of Degradation Effects on the High Frequency Noise of nMOSFETs 51
5.1 Introduction 51
5.2 Two-Port Noise Model 53
5.3 Analytical Noise Model 60
5.4 Degradation Model 63
5.5 Results and Discussion 66
5.6 Conclusion 70
5.7 Appendix 72
CHAPTER 6 A Thermal Noise Model for Fully Depleted SOI MOSFETs 87
6.1 Introduction 87
6.2 SOI Thermal Noise Model 88
6.3 Results and Discussion 94
6.4 Conclusion 99
6.5 Appendix 99
CHAPTER 7 Conclusion 112
Bibliography 115
作者簡介 120
Publication List 121

[1] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill 2001.
[2] A. van der Ziel, Noise in Solid State Devices and Circuits, Wiley 1986.
[3] T. H. Lee, Design of Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.
[4] J. -S. Goo, C. -H. Choi, A. Abramo, J. -G Ahn, Z. Yu, T. H. Lee, and R. W. Dutton, “Physical origin of the excess thermal noise in short channel MOSFETs,” IEEE Electron Device Letters, Vol. 22, No 2, Feb. 2001.
[5] E. Simoen, C. Clays, “On the flicker noise in sub-micron silicon MOSFETs,” Solid-State Electronics, Vol. 43, pp. 865-882, 1999.
[6] K. K. Hung, P. K. Ko, C. Hu, Y. C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistor,” IEEE Trans on Electron Devices, Vol. 37, pp. 654-665, March, 1990.
[7] G. Reimbold, “Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion – influence of interface states,” IEEE Transactions on Electron Devices, Vol. 31, No 9, pp. 1190-1195, Sept. 1984.
[8] F. H. Schottky, “On spontaneous current fluctuations in various electrical conductors,” Annalen der Physik, Vol. 57, pp. 541–567, 1918.
[9] T. Manku, “Microwave CMOS-device physics and design,” IEEE J. Solid State Circuits, Vol. 34, pp.277-284, March, 1999.
[10] C. H. Chen and M. J. Deen, “High frequency noise MOSFETs: I modelling,” Solid- State Electronics, Vol. 42, pp. 2069-2081, 1998.
[11] R. P. Jindal, “Hot-electron effects on channel thermal noise in file-line n-MOS field-effect transistors,” IEEE Transaction on Electron Devices, Vol. 33, pp.1395-1397, Sept. 1986.
[12] S. Tedja, J. Van del Spiegel, and H. Williams, “Analytical and experimental studies of thermal noise in MOSFETs,” IEEE Transaction on Electron Devices, Vol. 41, pp. 2069-2075, Nov. 1994.
[13] A. A. Abidi, “High-frequency noise measurements on FETs with small dimensions,” IEEE Transaction on Electron Devices, Vol. 33, pp. 1801-1805, Nov. 1986.
[14] P. Klein, “An analytical thermal noise model of deep-submicron MOSFET''s,” IEEE Electron Device Letters, pp. 399-401, 1999.
[15] A. J. Scholten, H. I. Tromp, L. E. Tiemeijer, R. van Langevelde, R. J. Havens, P. W. H. de Vreexte, R. F. Woerlee, A. H. Montree, and D. B. M. Klaassen, “Accurate thermal noise model for deep-submicron CMOS,” IEDM pp.155-158, Dec. 1999
[16] D. Triantis, A. Birbas, and D. Kondis, “Thermal noise modeling for short channel MOSFETs,” IEEE Transaction on Electron Devices, Vol. 43, pp. 1950-1955, Nov. 1996.
[17] G. Knoblinger, P. Klein, M. Tiebout, “A new model for thermal channel noise of deep-submicron MOSFETs and its application in RF-CMOS design,” IEEE J. Solid-State Circuits, Vol. 36, No. 5, pp.831-836, May 2001.
[18] C. -J. Sheu and S. -L. Jang, “A MOSFET gate current model with the direct tunneling mechanism,” Solid-State Electronics, Vol. 44, pp.1819-1824, 2000.
[19] W. Slotboom, G. Streutker, M. J. V. Dort, P. H. Woerlee, A. Pruijmboom, and D. J. Gravesteijn, "Non-local impact ionization in silicon device." in IEDM Tech. Dig., pp.127-130, 1991.
[20] M. -C. Hu, S. -L. Jang and C. -G. Chyau, “A physics-based short-channel current voltage model for lightly-doped-drain metal-oxide-semiconductor field-effect-transistors,” Jpn. J. Appl. phys., Vol. 36, pp. 3448-3459, 1997.
[21] Y. -S. Chen, T. -H. Tang and S. -L. Jang, “Modeling of hot carrier-stressed characterics of nMOSFET''s,” Solid-State Electronics, Vol. 39, pp. 75-81, 1996.
[22] S. -S. Liu, S. -L. Jang and C. -G. Chyau, “Compact LDD nMOSFET degration model," IEEE Trans. Electron Devices, Vol.45, pp.1538-1547, July, 1998.
[23] C. Enz, ”An MOS transistor model for RF IC design valid in all regions of operation,” IEEE Trans. Microwave Theory and Tech., Vol. 50, N0.1, pp. 342, 2002.
[24] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd-edition, New York McGraw-Hill, 1999.
[25] F. Gatta, E. Sacchi, F. Svelto, P. Vilmercati, and R. Castello, “A 2-dB noise figure 900-MHz differential CMOS LNA,” IEEE J. Solid-State Circuits, Vol. 36, pp. 1444–1452, 2001.
[26] A. Pascht, M. Grözing, D. Wiegner, and M. Berroth, ”Small-signal and temperature noise model for MOSFETs,” IEEE Trans. Microwave Theory and Tech., Vol. 50, No. 8, pp. 1927-1933, 2002.
[27] M. S. Obrecht, E. Abou-Allam, and T. Manku, “Diffusion current and its effect on noise in submicron MOSFETs,” IEEE Trans. Electron Devices, Vol. 49, No. 3, pp. 524-526, 2002.
[28] R. Kraus and G. Knoblinger, “Modeling the gate-related high-frequency and noise characteristics of deep submicron MOSFETs,” IEEE Custom Integrated Circuits Conf., pp. 209-212, 2002.
[29] R. Sarpeshkar, T. Delbruck, and C. A. Mead, ”White noise in MOS transistors and resistors,” Circuits and Devices, Vol. 9, No. 6, pp. 23-29, 1993.
[30] S. -L. Jang, S. -S. Liu, and C. -J. Sheu, “A compact LDD MOSFET I-V model based on nonpinned surface potential,” IEEE Trans. Electron Devices, Vol. 45, No. 12, pp. 2489-2498, 1998.
[31] A. van der Ziel and G. Bosman, “The effect of gate-voltage dependent mobility on thermal noise in MOSFETs,” Solid-State Electronics, Vol. 25, No. 6, pp. 525-527, 1982.
[32] G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectronics Reliability, Vol. 42, pp. 573-582, 2002.
[33] C. -H. Chen, M. J. Deen, Y. Cheng, M. Matloubian,” Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFETs from RF noise measurements” IEEE Trans, Electron Devices, Vol. 48, No. 12, pp. 2884 –2892, Dec. 2001.
[34] W. Jin, P. C. H. Chan, and J. Lau, “A physical thermal noise model for SOI MOSFET,” IEEE Trans. Electron Devices, Vol. 47, pp. 768-773, 2000.
[35] G. Zhang, H. Liao, R. Huang, M. Chan, X. Zhang, Y. Wang,” A closed-form thermal noise model of SOI MOSFETs for low noise application,” Semiconductor Device Res. Symp., 2001 Int., pp. 130–133, Dec. 2001.
[36] T. W. Macelwee, “SOI thin film fully depleted high performance devices,” SOS/SOI Technology Workshop, IEEE. Proceedings, pp. 76-78, Oct. 1988.
[37] W. Jin, W. Liu, C. Hai, P. C. H. Chan, and C. Hu, “Noise modeling and characterization for 1.5-V 1.8-GHz SOI low-noise amplifier,” IEEE Trans. Electron Devices, Vol. 48, No. 4, pp. 803-808, 2001.
[38] H. -F. Teng, S. -L. Jang, and M. H. Juang, “A unified model for high-frequency current noise of MOSFETs,” Solid-State Electronics, Vol. 47, Issue 11, pp. 2043-2048, Nov. 2003.
[39] M. -C. Hu and S. -L. Jang, “ An analytical fully-depleted SOI MOSFET model considering the effects of self-heating and source/drain resistance,” IEEE Trans. Electron Devices, Vol. 45, No. 4, pp. 797-801, 1998.
[40] Y. G. Chen, S. -Y Ma, J. B. Kuo, Z. Yu, R. W. Dutton, “An analytical drain current model considering both electron and lattice temperatures simultaneously for deep submicron ultrathin SOI NMOS device with self-heating,” IEEE Trans. Electron Devices, p. 899-906. 1995.
[41] C. H. Chen, M. J. Deen, M. Matloubian, Y. Cheng, “Extraction of channel thermal noise of MOSFETs,” Int. Conf. Microelectronics Test Structures (ICMTS), pp.42–47, 2000.
[42] Y. Cheng, C.-H. Chen, M. Matloubian and M. J. Deen, “High-frequency small signal AC and noise modeling of MOSFETs for RF IC design,” IEEE Trans. Electron Devices, p. 400-408, 2002.
[43] X. Xi, H. Wang, X. Zhang, Y. Wang, “A new physical I-V model of deep-submicron FD SOI MOSFETs for analogue/digital circuit simulation,” Solid-State and Integrated Circuit Tech. Int. Conf., pp. 435 –438, Oct. 1998.
[44] A. J. Scholten, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, Z. van Duijnhoven, V. C. Venezia, “ Noise modeling for RF CMOS circuit simulation,” IEEE Trans. on Electron Devices, Vol. 50, pp. 618 –632, March 2003.
[45] L. E. Larson, “Integrated circuit technology options for RFIC’s present status and future directions,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, pp. 387-399, March 1998.
[46] Y. Toyoshima, H. Iwai, F. Matsuoka, H. Hayashida, and K. Kanzaki, “Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET’s,” IEEE Trans. Electron Devices, Vol. 37, pp. 1496–1503, Aug. 1990.
[47] P. Heremans, R. Bellins, G. Groeseneken, and H. E. Maes, “Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET’s,” IEEE Trans. Electron Devices, Vol. 35, pp. 2194–2209, Nov. 1988.
[48] T. Wang, T. E. Chang, C. M. Huang, J. Y. Yang, K. M. Chang, and L. P. Chiang, “Structural effect on band-trap-band tunneling induced drain leakage in n-MOSFET’s,” IEEE Electron Device Lett., Vol. 16, pp. 566–568, Dec. 1995.
[49] Q. Li, J. Zhang, W. Li, J. S. Yuan, Y. Chen, A. S. Oates, “RF circuit performance degradation due to soft breakdown and hot-carrier effect in deep-submicrometer CMOS technology,” IEEE Trans. on microwave theory and techniques, Vol. 49, No. 9, pp. 1546 - 1551, 2001.
[50] P. R. Gray, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley & Sons, 1993, Chap11.
[51] C. C. Enz, F. Krummenacher and E. A. Vittoz, “An analytical MOS transistor Model valid in all regions of operation and dedicated to low-voltage and low-current applications,” special issue of the Analog Integrated Circuits and Signal Processing journal on Low-Voltage and Low-Power Design, Vol. 8, pp. 83-114, July 1995.
[52] T. Manku, “RF simulations and physics of the channel noise parameters within MOS transistors,” Proc. IEEE CICC, pp. 369-372, May 1999.
[53] D.R. Pehlke; M. Schroter, A. Burstein, M. Matloubian, M.F. Chang, “High-frequency application of MOS compact models and their development for scalable RF model libraries,” Proc. of the IEEE 1998, pp. 219 - 222 May 1998.
[54] X. Jin, J. –J. Ou, C. –H. Chen, W. Liu, M. J. Deen, P. R. Gray, Chenming Hu, “An effective gate resistance model for CMOS RF and noise modeling,” in IEDM Technical Digest,. pp. 961 – 964, Dec. 1998.
[55] W. S. Kwan, M. J. Deen, ”Hot-carrier effects on the scattering parameters of lightly doped drain n-type metal-oxide-semiconductor field effect transistor,” J. Vac. Sci. Technol. B 16(2), Mar/Apr 1998.
[56] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradation-model, monitor, and improvement,” IEEE Trans. Electron Devices, Vol. ED-32, pp. 375–385, Feb. 1985.
[57] E. F. Crabbe, J. M. C. Stork, G. Baccarani, M. V. Fischetti, and S. E. Laux, “The impact of nonequilibrium transport on breakdown and transit time in bipolar transistors,” in IEDM Tech. Dig., pp. 463–466, 1990.
[58] T. Wang, C. Huang, P. C. Chou, S. S.-S. Chung, and T.-E. Chang, “Effects of hot carrier induced interface state generation in submicron LDD MOSFET’s,” IEEE Trans. Electron Devices, Vol. 41, pp. 1618–1622, Sept. 1994.
[59] J. S. Goo, C. H. Choi, F Danneville, E Morifuji, H. S. Momose, Z. Yu, et al., “ An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs,” IEEE Trans. Electron Devices 47(12), pp. 2410-9, 2000.
[60] S. Naseh, M. J. Deen and O. Marinov, “Effects of hot-carrier stress on the RF performance of 0.18 um technology NMOSFETs and circuits,” IEEE 40th Annual International Reliability Physics Symposium, pp. 98-104, 2002.
[61] Y. Lin, M. Obrecht, T. Manku, “RF noise characterization of MOS devices for LNA design using a physical-based quasi-3-D approach,” IEEE Trans. Circuits and Systems 48(10), pp 972-984, 2001.
[62] D. P. Triantis, A. N. Birbas and S. E. Plevridis, “Induced gate noise in MOSFETs revisited: the submicron case,” Solid-State Electronics, 41(12), pp. 1937-1942, 1997