臺灣博碩士論文加值系統

晶片內網路架構是一種具彈性和伸縮性的基礎架構，因為其特性使得晶片內網路架構在多核心系統的設計中變得相當重要。晶片內網路架構中是由許多路由器來連結不同的核心，因為不同核心溝通時必須透過路由器來傳遞資料，所以資料傳遞路徑上的路由器個數越多，所帶來的延遲也相對的比較長。當晶片內網路的架構越來越大時，大量的路由器和緩衝器也會造成大量的功率消耗。動態電壓和頻率的調整技術可以為晶片內網路架構節省功率消耗。在本文中，我們設計了一個低延遲且低成本的緩衝器，該緩衝器用來當作不同頻率間溝通的介面。為了讓大家明白資料傳輸延遲與動態調整頻率的晶片內網路架構之間的關係，我們提供一個快速的內網路晶片時序模擬器，藉由蟲洞傳輸、封包傳輸路徑之間的關係以及緩衝器的特性，我們可以快速的計算出每一個封包到達目的地所需要的時間。我們的晶片內網路時序模擬器會考慮到實際晶片內網路架構硬體的特性，也會考慮封包在硬體上傳輸所需的延遲時間，所以我們計算出來的時間十分精確。根據我們最後實驗數據顯示，我們的晶片內網路時序模擬器計算出來的結果和時脈精確模型所模擬的結果一模一樣，並且我們晶片內網路時序模擬器所需的模擬時間相對於時脈精確模型來的短，我們的晶片內網路時序模擬器最快可以比時脈精確模型快上96倍。

Network-on-Chip (NoC) has become an essential interconnect technology for many-core systems because of its scalable and flexible infrastructure. However, the router-based NoC structure has long latency (large hops) between connected cores. Also, large power consumption is spent on
routers and FIFOs. To address the later issue (for lower power), a Dynamic Voltage and Frequency Fcaling (DVFS) scheme is proposed for traditional NoC.
In this thesis, we first designed a low-cost low-latency synchronous FIFO to support DVFS in NoC. Then, in order to better understand the impact of latency introduced by NoC (and DVFS at lower frequency), we proposed a quick timing
simulator for DVFS NoC.
The simulator can take several important factors of a NoC into account: worm-hole switching, inter-traffic relations and speed difference between FIFOs.
In the experiment, the proposed simulator can correctly calculate all timings with a speedup up to 95 times as
compared with a cycle-accurate model.

1 Introduction 7
1.1 Related work 7
1.2 Objective and Motivation 8
1.3 Thesis Organization 9
2 Background of NoC Architecture 10
2.1 2-D Mesh NoC Architecture 10
2.2 Basic unit for 2-D Mesh NoC 11
2.3 Mechanism of Packet Transmission 12
2.3.1 Packet Description 13
2.3.2 NoC Transaction and Transport Protocol 13
2.3.3 Arbitration and Worm-hole Switching 15
2.3.4 X-Y Routing 18
3 Synchronizing FIFO for NoC 19
3.1 FIFO Architecture 20
3.2 Cell Implementation 23
3.3 Latency and Throughput Analysis 27
3.4 FIFO Test and Synthesis result 29
4 NoC Timing Simulator 30
4.1 Manual of NoC Timing Simulator 30
4.2 Calculation procedures 32
4.3 Definition 35
4.4 The Method of Calculating Packet Arrival Time 37
4.4.1 Formula of header arrival time 38
4.4.2 Formula of flits arrival time 38
4.5 Special Case of Packet Transmission 41
5 Verification and Experiment Result 42
5.1 Environment Setting and Verification Flow 42
5.2 Testbench of Packets 44
5.3 Result 45
6 Conclusion and Future Work 48
6.1 Conclusion 48
6.2 Future Work 48

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