跳到主要內容

臺灣博碩士論文加值系統

(216.73.216.106) 您好!臺灣時間:2026/04/04 14:45
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:張嘉展
研究生(外文):Chia-Chan Chang
論文名稱:利用功率結合電路之寬頻功率放大器
論文名稱(外文):Broadband Power Amplifier Using Power Combining Circuit
指導教授:黃育賢
口試委員:吳民首
口試日期:2014-07-12
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所 電子電腦與通訊產業研發碩士專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:61
中文關鍵詞:互補式金屬氧化電晶體寬頻功率放大器並聯式功率結合變壓器匹配網路臨界通道洩漏比
外文關鍵詞:Complementary Metal Oxide SemiconductorBroadband Power AmplifierParallel Power CombiningTransformer Matching NetworkAdjacent Channel Leakage Ratio
相關次數:
  • 被引用被引用:0
  • 點閱點閱:384
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文採用互補式金屬氧化電晶體0.18μm(CMOS 0.18μm)製程之寬頻功率放大器,使用疊接(cascode)結構,以增加電路的操作崩潰電壓;利用並聯式功率結合器,將兩路的功率放大器做功率結合,以提高輸出功率,而透過具有寬頻操作特性的變壓器匹配網路,使功率放大器可以操作在寬頻帶。汲極端電壓為4.1伏特的狀態下,此功率放大器在1.65~2.45GHZ時的1dB壓縮點輸出功率(1 dB compression point output power;OP1dB)為26~27.6dBm,功率附加效率(Power Added Efficiency;PAE)為15~22%,而增益為12.4dB~32dB。在線性功率方面,以峰均功率比(Peak-to-Average Power Ratio;PAPR)為2.7dB的寬頻分碼多工(Wideband Code Division Multiple Access;WCDMA)調變訊號作測試,在中心頻率平移5MHz下,工作頻率1.65~1.95GHz通過臨界通道洩漏比(Adjacent Channel Leakage Ratio;ACLR)小於-36dBc規範的輸出功率皆在22.8dBm之上,而工作頻率1.65~2.45GHz通過ACLR小於-33dBc規範的輸出功率在23.3dBm以上。
無線行動通訊系統未來面臨到的是更多頻段的應用,故寬頻功率放大器可以節省以往積體化多顆窄頻PA所佔據的晶片面積,以及減少射頻發射機前端電路的設計複雜度,使射頻發射機整合的成功率增加;擁有高功率輸出的系統,意味著此系統能夠涵蓋更廣的應用範圍;而擁有高的線性輸出,則是因應未來調變訊號的PAPR及頻寬日益增加的趨勢。

This thesis proposed broadband power amplifier using Complementary Metal Oxide Semiconductor 0.18μm process. The cascade architecture was used to increase operating breakdown voltage and parallel power combiner united two power stages to increase output power. According broadband characteristic of transformer matching network, the power amplifier could work in broadband. When this power amplifier’s drain voltage was 4.1 Volt, the measured output 1-dB compressed power, power added efficiency and power gain in 1.65~2.45GHz were 26~27.6dBm, 15~22% and 12.4~32dB.
At the mention of linear power, a Wideband Code Division Multiple Access modulated signal with 2.7 dB Peak-to-Average Power Ratio (PAPR) was used to test. Under the frequency offset is 5 MHz from center frequency, the power amplifier’s output power in 1.65~1.95GHz passing the Adjacent Channel Leakage Ratio(ACLR) less than -36dBc was more than 22.8dBm, and in 1.65~2.45GHz passing the ACLR less than -33dBc was more than 23.3dBm.
Wireless mobile communication system is faced with multi-band application, so broadband power amplifier can save the size occupied by integrating many narrow band power amplifiers in a chip before, decrease the design complexity of ratio frequency transmitter from end circuit therefore. A system with high output power means this system application range is wider; with high linear output power is to respond ever-growing modulated signal PAPR.


目 錄
中文摘要 i
英文摘要 ii
致謝 iii
目錄 vi
圖目錄 vii
表目錄 ix
第一章 序論 1
1.1 概論及研究動機 1
1.2 篇章結構 3
第二章 功率放大器介紹 4
2.1 放大模式功率放大器類別及特性 4
2.1.1 A類放大器 4
2.1.2 B類放大器 8
2.1.3 AB類放大器 10
2.1.4 C類放大器 11
2.2 功率放大器重要參數 12
2.2.1 輸出功率 13
2.2.2 線性度 13
2.2.2.a 1dB增益壓縮點 14
2.2.2.b 鄰近通道洩漏比 15
2.2.3 效率 16
2.2.4 穩定度 17
第三章 寬頻架構放大器暨功率結合變壓器探討 21
3.1 平衡式放大器 21
3.2 分佈式放大器 22
3.3 電阻(有損)匹配放大器 22
3.4 負回授放大器 23
3.5 變壓器匹配電路 24
3.6 串聯式功率結合變壓器 26
3.7 並聯式功率結合變壓器 27
第四章 具並聯式功率結合器之寬頻放大器實現 30
4.1 電路架構說明 30
4.2 電路設計流程 37
4.3 量測考量 39
4.4 量測步驟 39
4.4.1 直流分析 39
4.4.2 小訊號量測 40
4.4.3 大訊號量測 41
4.5 模擬與量測結果 42
第五章 結論 57
參考文獻


[1] Kevin T. Kornegay et al., “A Fully-Integrated High-Power Linear CMOS
Power Amplifier With a Parallel-Series Combining Transformer,” IEEE J. of Solid -State Circuits, vol. 47, no. 3, pp.599-614, Mar. 2012.

[2] Kevin T. Kornegay et al., “A Linear Multi-Mode CMOS Power Amplifier
With Discrete Resizing and Concurrent Power Combining Structure,” IEEE J. OF Solid-State Circuits, vol. 46, no. 5, pp.1034-1048, May 2011.

[3] Tsu-Jae King Liu et al., “Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off,” IEEE J. of Solid-State Circuits, vol. 43, no. 3, pp.600-609, Mar. 2008.

[4] Patrick Reynaert et al., “Analysis and Optimization of Transformer-
Based Power Combining for Back-Off Efficiency Enhancement,” IEEE Transactions on Microwave Theory and Techniques. vol. 60, no. 4, pp.825-835, Apr. 2013.

[5] G. B. YUNDT, ” Seres- or Parallel-Connected Composite Amplifiers,” IEEE Transactions on Power Electronics. vol. PE-1, no. 1, pp.48-54, Jan. 1986.

[6] T. Cegielski and R. Matuszewski, “The design of medium powerC-band
balanced amplifiers,” in Proc. 15th Int. Conf. Radar Wireless Communications, Warsaw, Poland, May 2004, pp. 107–110.

[7] W. S. Percival, “Thermionic valve circuits,” British Pat, 460562,
1936.

[8] E. W. Strid and K. R. Gleeson, “A DC–12 GHz monolithic GaAs FET
distributed amplifier,” IEEE Trans. Microw. Theory Tech., vol. MTT-30,
no. 7, pp. 969–975, July 1982.

[9] K.W. Eccleston, “Compact dual-fed distributed power amplifier,” IEEE
Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 825–831, Mar. 2005.

[10] T. Arell and T. Hongsmatip, “A unique MMIC broad-band power
amplifier approach,” IEEE J. Solid-State Circuits, vol. 28, no. 10, pp.
1005–1010, Oct. 1993.

[11] X. Zhu, X. Chen, and J. Ling, “2–6 GHz GaAs MMIC power amplifier,”
in Proc. Int. Microwave and Millimeter Wave Technology Conf., Beijing,
China, Sep. 2000, pp. 134–137.

[12] Jun-De Jin and Shawn S. H. Hsu, “A 0.18- μ m CMOS Balanced Amplifier
for 24-GHz Applications,” IEEE J. of Solid-State Circuits, vol. 43, no. 2, pp.440-445, Feb. 2008.

[13] Gary Zhang, Shiaw Chang, and Ziv Alon, ” A high performance Balanced Power Amplifier and Its Integration into a Front-end Module at PCS Band,” in Proc. Radio Frequency Integrated Circuit Symposium, USA, June 2007, pp.251-254.

[14] R. S. Engelbrecht and K. Kurokawa, “A wideband low noise L-band
balanced transistor amplifier,” Proc. IEEE, vol. 53, no. 3, pp. 237–247, Mar. 1965.

[15] K. Kurokawa, “Design theory of balanced transistor amplifiers,” Bell
Syst. Tech. J., vol. 44, pp. 1675–1698, Oct. 1965.

[16] Cioffi, K.R., “Broad-Band Distributed Amplifier Impedance-Matchng Techniques,” IEEE Transactions on Microwave Theory and Techniques. vol. 37, no. 6, pp.1870-1876, Dec. 1989.

[17] R.B. GOLD, “The Matched Feedback Amplifier:
Ultrawide-Band Microwave Amplification with GaAs MESFET’S,” IEEE Transactions on Microwave Theory and Techniques. vol. 28, no. 4, pp.285-294, Apr. 1980.

[18] Henry Shu-Hung Chung et al., “Characterization of Coreless Printed Circuit Board (PCB) Transformers,” IEEE Transactions on Power Electronics. vol. 15, no. 6, pp.1275-1282, Nov. 2000.

[19] Joy Laskar et al., ” Power-Combining Transformer Techniques for
Fully-Integrated CMOS Power Amplifiers,” IEEE J. of Solid-State Circuits, vol. 43, no. 5, pp.1064-1075, MAY. 2008.

[20] Irdad Sowlati and Domine M. W. Leenaerts, “A 2.4-GHz 0.18-μm CMOS self-biased cascode poweramplifier” IEEE Journal of Solid-State Circuits, vol. 38, no. 8, Aug. 2003.

[21] P. C. Wang et al., “A 2.4-ghz fully integrated transmitter front end with +26.5-dBm on-chip CMOS power amplifier,” in IEEE Radio Frequency Integrated Circuits Symposium, 2007.

[22] Chang-Ho Lee et al., “A Highly Efficient GSM/GPRS Quad-band CMOS PA Module,” in IEEE Radio Frequency Integrated Circuits Symposium, 2009.

[23] J. Stevenson Kenney, ” A Cascode Feedback Bias Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology,” IEEE Transactions on Microwave Theory and Techniques. vol. 61, no. 2, pp.890-901, Feb. 2013.

[24] Bumman Kim et al., “Linearization of CMOS Cascode Power Amplifiers
Through Adaptive Bias Control,” IEEE Transactions on Microwave Theory and Techniques. vol. 61, no. 12, pp.4534-4543, Dec. 2013.

[25] Haitao Zhang, Huai Gao, and Guann-Pyng Li, “Broad-Band Power Amplifier With a Novel Tunable Output Matching Network,” IEEE Transactions on Microwave Theory and Techniques. vol. 53, no. 11, pp.3606-3614, Nov. 2005.

[26] Huei Wang et al., “A High-Efficiency, Broadband CMOS Power
Amplifier for Cognitive Radio Applications,” IEEE Transactions on Microwave Theory and Techniques. vol. 58, no. 12, pp.3556-3565, Dec. 2010.

[27] Tyson S. Wooten and Lawrence E. Larson ,” A Decade Bandwidth, Low Voltage, Medium Power Class B Push-Pull Si/SiGe HBT Power Amplifier Employing Through-Wafer Vias,” in IEEE Radio Frequency Integrated Circuits Symposium, San Diego, APR, 2008, pp.519-522.

[28] Svelto, F. et al., ” A 1.4 GHz = 2 GHz wideband CMOS class-E Power Amplifier delivering 23dBm peak with 67% PAE,” in IEEE Radio Frequency Integrated Circuits Symposium, 2005, pp.425-428.

[29] Bumman Kim et al., “A 30.8-dBm Wideband CMOS Power Amplifier
With Minimized Supply Fluctuation,” IEEE Transactions on Microwave Theory and Techniques. vol. 60, no. 6, pp.1658-1666, June. 2012.

[30] Giuseppe Palmisano et at., ” A 25 dBm Digitally Modulated CMOS
Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control.” IEEE Journal of Solid-State Circuits, vol. 44, no. 7, pp.1883-2009, July 2009.

[31] Chengzhou Wang, Member, Mani Vaidyanathan, and Lawrence E. Larson, “A Capacitance-Compensation Technique for Improved Linearity in CMOS Class-AB Power Amplifiers,” IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp.1927-1937, NOV. 2004.

[32] 王明發,行動手機設備之原理解析與電路實現,碩士論文,國立臺北科技大學,台北,2011

[33] 林亞緯,利用串聯式與並聯式功率結合變壓器之高功率放大器,碩士論文, 國立臺北科技大學,台北,2011

[34] 黃仕昕,具並聯式功率結合器之多模功率放大器,碩士論文, 國立臺北科技大學,台北,2012


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top