臺灣博碩士論文加值系統

靜態隨機存取記憶體(SRAM)大量被使用在系統單晶片中，且應用於高效能的處理器、IoT、AI等，且伴隨著製程技術不斷的進步而漏電流會越來越大，使得SRAM操作在次臨界電壓之設計具有挑戰性，像是傳統6T有讀干擾(Read Disturb)、半選擇(Half-Select)問題；而RD-8T增加額外讀取路徑，看似解決傳統6T的讀干擾問題，但RD-8T為單端讀取設計，因此讀取位元線(RBL)容易受到漏電流的影響，使得感測放大器判別錯誤。然而為了使SRAM能在低電壓操作更穩定，因此，本論文提出一個PNN-12T SRAM之cell設計可操作於次臨界電壓，使用控制訊號電路(Control Signal Circuit)設計來輔助寫、讀與保持模式之低電壓操作，當寫入操作模式時，控制訊號電路會將中間跨耦合(cross couple)反相器切斷下拉的路徑，且同時提供額外的放電路徑來改善寫入的能力(write ability)；另外，在寫的操作模式時，控制訊號電路提供額外的充電路徑，使得該半選擇細胞元(cell)所儲存的節點(Q/QB)更穩定；當讀取操作模式時，控制訊號電路會將中間跨耦合(cross couple)反相器開啟下拉的路徑，且讀取的放電路徑不會經過細胞元(cell)中的儲存節點來消除讀的干擾。除此之外，在1Kb記憶體細胞元面積下，提出12顆電晶體的佈局設計可以比FD-10T提出的10顆電晶體的面積節省6.71%，與PCA-12T的面積節省15.72%，而本設計為1Kb SRAM macros (32 rows * 32 columns)的架構由TSMC-40nmGP製程實現，在250mV，能量消耗所提出設計PNN-12T SRAM比DFL-10T少了75.34%，在350mV，能量消耗所提出設計PNN-12T SRAM比PCA-12T少了83.25%。

There has large usage of low-power SRAM in System-on-Chip (SoC) for high performance processor, IoT and AI applications. With the continuous advancement of process technology, the transistor has large leakage currents, so that the design of sub-threshold operation SRAM becomes more challenge, and its area cost becomes bigger. For example, the 6T SRAM cell suffered the read disturb and half-select issue. RD-8T added external read path, which seemed to solve the read disturb problem of the 6T. However, it had the single-end structure, and the read bitline (RBL) affected by leakage currents, which made the sensing amplifier identify failure. In order to make the sub-threshold operation SRAM more stable and much low power, a PNN 12T-cell SRAM architecture for sub-threshold operation is proposed. The control signal circuit is used to reduce operation power in write/read and hold modes. When the SRAM is in writing mode, the porposed control signal circuit can cut the pull-down path of the cross couple inverter, and makes the bit cell be easier to write the data. Even more, the proposed circuit provides an extra discharge path to improve the write-ability at the same time. In addition, the proposed control circuit provides a charging path to improve the stability of storage node for the half-selected cell. When the read mode, the control circuit will open the pull-down path of the cross couple inverter, and the read discharge path will not pass through the storage node of the cell to eliminate the read disturb. The proposed design with 1Kb memory can achieve 6.71% and 15.72% area saving compared with FD-10T and PCA-12T. The 1-Kb SRAM macros (32 rows*32 columns) architecture is implemented based on TSMC-40nm GP process. At 250mV, the energy consumption of our work is less than the DFL-10T by 75.34%. At 350mV, the energy consumption of our work is less than the PCA-12T by 83.25%.

摘要 i
Abstract ii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1-1 研究動機與目的 1
1-2 功率消耗分析 2
1-3 設計流程 7
1-4 論文架構 9
第二章 靜態隨機存取記憶體相關介紹 10
2-1 介紹 10
2-2 SRAM周邊電路 13
2-2.1 解碼器 15
2-2.2 預充電路 16
2-2.3 寫入驅動器 17
2-2.4 感測放大器 18
2-2.5 控制電路 19
2-3 次臨界記憶體之相關文獻 20
2-3.1 傳統6T SRAM設計 20
2-3.2 RD-8T SRAM設計[8] 24
2-3.3 FD-10T SRAM設計[9] 27
2-3.4 PPN-10T SRAM設計[11] 31
2-3.5 PCA-12T SRAM設計[10] 34
2-3.6 DFL-10T SRAM設計[12] 37
2-3.7 Differential-10T SRAM設計(雲科) 40
第三章 提出的12T SRAM記憶體設計 44
3-1 提出12T之工作原理與設計 44
3-1.1 寫模式操作 46
3-1.2 讀模式操作 47
3-1.3 控制訊號電路(Control Signal Circuit，CSC) 48
3-1.4 寫入操作之半選擇狀態分析 51
第四章 晶片實現驗證 54
4-1 模擬結果 54
4-2 結論 64
參考文獻 65
附錄 67

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