臺灣博碩士論文加值系統

通道損耗(Channel loss)是影響高速輸入/輸出信號表現的主要因素。某些平台設計指南中清楚地指出印刷電路板(PCB)損耗的要求。在初期設計階段(對於PCB材料選擇)，平台設計人員想要有準確、有效率的插入損耗(insertion loss)量測，以符合通道的要求，因為PCB材料對平台成本的貢獻很大。近年來，高速應用變得更加普遍，使的印刷電路板設計預算更為嚴苛，並增加PCB材料的條件。如果PCB材料選擇不當，可能導致昂貴的過度設計，或是增加平台效能上的風險。插入損耗是廣泛用以選擇合適PCB材料的指標之一。然而，許多因素影響著插入損耗測量，像是去嵌入法(de-embedding)、探針足跡的設計(probes footprint designs)、測量的技術、測試板疊構設計等等。即使使用相同測量方法，具有不同的疊構設計將導致不同的材料損耗值。
在本文中，一項關於插入損耗表徵的PCB設計和分析優化的綜合研究使用不同的方法學進行了驗證。 Delta-L方法學結果與2x-Thru和Thru-line結果相關，並且將其用於PCB電氣特性描述是很好的。手持式探針量測和SMA的結果是一致的，使用手持式探針可減少測量時間和人力資源，在量測的準確性與10 inch和5 inch相比，提出了手持式探針使用4 inch和2 inch的去嵌入結構來優化PCB測試版的尺寸。

Channel loss is a dominant factor for the signaling performance of high-speed I/O’s. Some platform design guides clearly specify the printed-circuit board (PCB) loss requirement. During the initial design stage, PCB material selection, platform designers would like to have the accurate and efficient insertion loss measurement to meet the channel requirement, because the PCB material contributes largely to the platform cost. In recent years, high speed applications become more and more popular resulting in the rigorous printed circuit board design budget and increasing the requirement of PCB material. An improper selection of PCB material may lead to either a costly over design or an increased risk of platform performance. Insertion loss is one of widely employed indicator to select proper quality of PCB material. However, there are a lot of factors affecting insertion loss measurement quantity such as de-embedding methods, probes footprint designs, measurement arts, test board stack-up designs and et al. Having different stack-up design leads to distinct material loss values even with same measurement methodology.
In this paper, a comprehensive study on PCB design and analysis optimization for insertion loss characterization were validated by industry metrologies. Delta-L methodology result is correlated with 2x-Thru results and it is good to utilize this for PCB electrical characterization. The de-embedding structure by 4 inch and 2 inch by handheld probes is proposed in the accuracy, efficiency and compact test coupon size, compared with 10 inch with 5 inch by SMA.

目錄
中文摘要 I
英文摘要 II
致謝 III
目錄 IV
圖目錄 V
表目錄 VI
第一章 序論 1
第一節 PCB損耗量測參考平面的重要性 2
第二章PCB損耗量測之方法學 5
第一節 業界去嵌入(DE-EMBEDDING)方法學介紹 5
1. Thru-Reflect-Line(TRL) 5
2. 2X through (2X-thru) 6
3. Thru-line 7
4. Intel Delta-L 9
第三章 量測設計介紹 11
第四章PCB損耗量測的設計與分析優化 14
第一節 DELTAL-L和業界方法學的比較與分析 14
第二節 手持式探針與傳統式同軸連接器比較 17
第三節 探討與分析有效的去嵌入長度 24
第五章 結論 26
參考文獻 26
圖目錄
第一章
圖1- 1參考平面 3
圖1- 2 Via stub 的影響 4
圖1- 3有無via stub量測的比較 4
圖1- 4 Trace only 區域 5
第二章
圖2- 1 TRL 測試架構 6
圖2- 2 2X through 架構 7
圖2- 3 Thru-line 架構 8
圖2- 4 Delta-L 架構 9
圖2- 5 Delta-L 演算法圖示 10
圖2- 6每單位長度損耗 10
第三章
圖3- 1測試板架構Test Coupon 11
圖3- 2 Probing Solutions 12
圖3- 3量測架構 13
第四章
圖4- 1不同業界方法學之比較 17
圖4- 2 3L驗證方法 18
圖4- 3 Insertion Loss Comparison by Probe 19
圖4- 4 Comparison of Trace Impedance 20
圖4- 5 10 inch Trace Impedance on SMA Side 20
圖4- 6 Differential pair傳輸線模型 21
圖4- 7 PCB切片位置 21
圖4- 8切片圖 22
圖4- 9切片報告與模擬比對 23
圖4- 10 Gerber Layout on Layer 6 23
圖4- 11 PCB壓合 24
圖4- 12 Insertion Loss Comparison by Probe 26

表目錄
第三章
表3- 1測試板測試方案 12
表3- 2量測設定 13
第四章
表4- 1不同方法學 14
表4- 2 Probing Comparison 17
表4- 3 Effective Routing Comparison 25

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[2]H. Barnes, E. Bogatin, J. Moreira, J. Ellison, et al. “A NIST Traceable PCB Kit for Evaluating the Accuracy of DeEmbedding Algorithms and Corresponding Metrics, ”DeisgnCon 2018.
[3]X. Ye, J. Fan and J. Drewniak, "New De-embedding Techniques for PCB Transmission-Line Characterization", DesignCon 2015.
[4]IEEE P370 open-source 2x-Thru de-embedding code, https://gitlab.com/IEEE-SA/ElecChar/P370.
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[6]X. Ye, J. Fan and J. Drewniak, "New De-embedding Techniques for PCB Transmission-Line Characterization", to be published in Proc. Of DesignCon 2015.
[7]Thru-line: Bichen Chen, Xiaoning Ye, Bill Samaras, Jun Fan, A novel de-embedding method suitable for transmission-line measurement, 2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC)
[8]Delta-L Methodology for Electrical Characterization, Rev. 330223-001 http://www.intel.com/content/www/us/en/processors/xeon/delta-l-methodology-for-electrical-characterization-guide.html
[9]J. Hsu, T. Su, K. Xiao, X. Ye, S. Huang, Y. Li, “Delta-L 2.0 Methodology for Efficient PCB Trace Loss Characterization”, Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2014 9th International.
[10]C. Lin, G.H. Shiue, J. Hsu, T. Su, J. Lin, Cloud. Lai, “PCB Design and Analysis Optimization for Insertion Loss Characterization by Validating Industry Metrologies”, Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2017 12th International.