臺灣博碩士論文加值系統

本論文提出一個具有降低參考電壓抖動影響之十二位元連續漸進式(successive-approximation register, SAR)類比數位轉換器(analog-to-digital converter, ADC)。
為達要壓抑參考電壓抖動之影響，本論文使用了額外的電容陣列與四端輸入比較器(four-input comparator)，透過與主要電容陣列切換相同極性的方式，切換額外電容陣列的最高有效位元(Most significant bit, MSB)與MSB-1兩位元，並將此兩組含有參考電壓抖動影響之電容陣列在比較器上做相減，以達到壓抑4倍量的參考電壓抖動之影響，即為放寬了兩位元的參考電壓抖動規格之需求。
為驗證本電路，此架構使用90奈米1P9M互補式金氧半導體製程製作，核心電路面積為443.38 x 198.1um2，在1伏特電源電壓及3百萬赫茲取樣頻率操作下，此晶片在低頻率訊號輸入時實現之SNDR為62.69dB，其對應的ENOB為10.12-bit，功率消耗為38.88微瓦，而等效的figure of merit (FoM)為11.6fJ/conversion-step。此外，此晶片並具有降低參考電壓抖動影響之功能，能壓抑約3倍量的參考電壓抖動之影響。

This thesis presents a 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with suppressing the influence of reference voltage’s ripples.
The proposed ADC uses an extra capacitance array and a four-input comparator to suppress the influence of reference voltage’s ripples. The most significant bit (MSB) and MSB-1 of the extra capacitance array are switched to the same polarity with that of the main capacitance array. Then, the comparator is going to subtract the two voltages of the two capacitance arrays, which include the reference voltage’s ripples, so that the ADC can suppress the influence of the reference voltage’s ripples 4 times. That is, the proposed ADC releases 2-bit requirement of the reference voltage’s ripples.
The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 443.38 x 198.1um2. At 1 supply voltage and 3MS/s sampling rate, the ADC achieves the SNDR of 62.69dB and the corresponding ENOB is 10.12-bit at the input signal with low frequency. It consumes the power consumption of 38.88µW, resulting in a figure of merit (FoM) of 11.6fJ/conversion-step. In addition, the ADC has the feature of suppressing the reference voltage’s ripples, which could reduce the influence of the reference voltage’s ripples 3 times roughly.

Abstract ii
Content iii
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 Architecture Selection 2
1.2 Performance Metrics of SAR ADC 4
1.2.1 Nyquist Criterion 4
1.2.2 Resolution 4
1.2.3 Quantization Error 5
1.2.4 Offset and Gain Error 6
1.2.5 Differential Nonlinearity 6
1.2.6 Integral Nonlinearity 7
1.2.7 Signal-to-Noise Ratio 7
1.2.8 Signal-to-Noise and Distortion Ratio 8
1.2.9 Spurious-Free Dynamic Range 8
1.2.10 Effective Number of Bits 8
1.2.11 Figure of Merit 9
1.3 Target Specifications 9
Chapter 2 Successive Approximation Register ADC Overview 11
2.1 Introduction 11
2.2 Operation Procedure of Conventional SAR ADC 12
2.3 Considerations of Sample and Hold 13
2.3.1 On-Resistance of MOS Switch 14
2.3.2 Charge Injection 15
2.3.3 Clock Feedthrough 15
2.3.4 kT/C Noise 16
2.3.5 Sampling Speed 17
2.4 Considerations of Capacitive DAC 17
2.4.1 DAC Parasitic Capacitance 18
2.4.2 DAC Capacitor Mismatch 19
2.4.3 Settling Time 20
2.5 Considerations of Comparator 21
2.5.1 Input Offset 21
2.5.2 Kickback Noise 22
2.6 Considerations of SAR Control Logic 23
2.7 Considerations of Reference Voltage Ripple 25
2.8 Summary 27
Chapter 3 Circuit Design Considerations 29
3.1 Differential ADC 29
3.2 Reference Ripples/Noise Analysis 30
3.3 Sample and Hold 36
3.4 Comparator 37
3.5 Low-Pass Filter 38
3.6 SAR Control Logic 38
3.7 CDAC Switching Energy 39
3.8 Summary 41


Chapter 4 Circuit Implementation of Successive Approximation Register ADC 43
4.1 Architecture of Proposed SAR ADC 43
4.2 Design of Sample and Hold 46
4.3 Design of Capacitive DAC 47
4.4 Design of Four-Input Comparator 49
4.5 Design of Redundancy 51
4.6 Pre-Layout and Post-Layout Simulations 55
4.7 Summary 57
Chapter 5 Measurement Results 58
5.1 Measurement Environment Setup 58
5.2 Chip Micrograph 59
5.3 Static Performance 60
5.4 Dynamic Performance 62
5.5 Performance Summary and Comparison 64
5.6 Summary 66
Chapter 6 Conclusion and Future Work 67
6.1 Conclusion 67
6.2 Future Work 67
Bibliography 68

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