臺灣博碩士論文加值系統

本篇論文實現了一個利用動態時間窗來控制相位資訊的全數位鎖相迴路，實作上提出雙模式雙路徑的操作來達成快速鎖定與低時脈抖動的特性。補償相位的路徑利用動態改變除數的方式，而頻率的修正則由前饋路徑直接調變數位振盪器。除此之外，雙模式的設定使得迴路在鎖定後能切換至窄頻寬且妥善設計其阻尼係數。由於在鎖定過程中，鎖相迴路維持在一個較小的相位誤差，因此鎖定時間可有效地縮短；可程式化的數位濾波器設計也使得鎖定後的效能能夠獲得控制。在電路層面上，使用不對稱延遲單元減少在時序數位轉換器的功耗與面積，後端具有錯誤校正的編碼器可用來減輕時序放大電路的規格要求；數位振盪器的部分，則是選擇具有較細解析度與較佳相位雜訊之電感電容架構。因此，提出之系統架構可實現一低時脈抖動與快速鎖定的全數位鎖相迴路。
使用台積電0.18微米製程設計一應用於2.4 GHz頻帶之全數位頻率合成器。在5-25 MHz的跳頻距離下，鎖定時間皆小於5 us；中心頻率為2.49 GHz時，量測到的時脈抖動為1.93 ps，相位雜訊於100 kHz與1 MHz頻率偏移下分別為-79.6 dBc/Hz和-112.7 dBc/Hz，參考頻率突波於5 MHz頻率偏移下低於-50 dBc。整個鎖相迴路操作在1.8 V共花費10.35 mA電流，晶片面積為1.8 mm2。

This thesis presents an all-digital phase-locked loop (ADPLL) featuring a dynamic phase compensation by a set of the auxiliary timing window. When frequency hopping occurs, the compensation scheme is implemented in both frequency and phase domain for fast settling. The detected phase error is continuously sent to the divider chain which changes the divider ratio, and directly modulates the frequency of the digital-controlled oscillator (DCO) through a digital feed-forward path at the same time. The proposed method allows the ADPLL maintaining a small phase error throughout the frequency acquisition process; thereby reducing setting time. Because of the switching mode operation, the mentioned techniques can solve the trade-off between low jitter and fast lock. An uneven-step time-to-digital converter (TDC) with an error correction encoder is implemented to relax circuit design and save power consumption. The DCO adopts the LC-based architecture because it has the finer tuning gain and better phase noise performance. The proposed ADPLL is implemented to optimize timing jitter and lock time.
The proposed technique is incorporated in the design of a 2.4 GHz ADPLL and fabricated in the TSMC 0.18 um CMOS technology. With less than 5 us lock time in hopping frequency from 5 MHz to 25 MHz, the measured rms jitter from a 2.49 GHz carrier is about 1.93 ps. The phase noise at 100 kHz and 1 MHz is -79.6 dBc/Hz and -112.7 dBc/Hz, respectively. The reference spur at 5 MHz offset is under -50 dBc. The whole circuit dissipates 10.35 mA from a 1.8 V supply and the chip area is 1.8 mm2.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Overview 2
Chapter 2 Introduction to All-Digital Phase-Locked Loops (ADPLLs) 3
2.1 The Basics of Analog Phase-Locked Loop (PLL) 3
2.2 State of the Art ADPLLs 5
2.3 The Basics of ADPLL Building Blocks and Modeling 7
2.3.1 Phase/Frequency Detector (PFD) and Time-to-Digital Converter (TDC) 8
2.3.2 Digital Loop Filter (DLF) and Digital-Controlled Oscillator (DCO) 9
2.3.3 Divider 11
2.4 Summary 13
Chapter 3 A Fast-Locking ADPLL using Dynamic Phase Control 14
3.1 Introduction 14
3.2 Principle of the Proposed Method 16
3.2.1 Background 17
3.2.2 Phase Error Compensation 18
3.2.3 Proposed ADPLL Architecture 20
3.2.4 Control Mechanism of DLF 23
3.3 Linear Model Analysis of Proposed ADPLL 24
3.3.1 ADPLL in Frequency Acquisition Mode 24
3.3.2 ADPLL in Phase Tracking Mode 26
3.3.3 Stability Analysis 28
3.3.4 Transient Behavior 30
3.3.5 Output Spur 31
3.3.6 Phase Noise and Jitter 32
3.3.7 Design Example and Behavior System Simulation 36
Chapter 4 Design and Implementation of the ADPLL 42
4.1 Circuit Implementations 42
4.1.1 PFD and TDC 42
4.1.2 Divider 47
4.1.3 DCO 50
4.1.4 DLF and Delta-Sigma Modulator (DSM) 57
Chapter 5 Experimental Results 59
5.1 Test Setup 59
5.2 Chip Pin Configurations and Printed Circuit Board Design 60
5.2.1 Chip Pin Configurations 60
5.2.2 Printed Circuit Board (PCB) Design 61
5.3 The DC supply Regulator 62
5.4 Experimental Results 63
5.4.1 Lock Time Measurement Results 63
5.4.2 Timing Jitter Measurement Results 65
5.4.3 Phase Noise and Reference Spur Measurement Results 66
5.5 Summary of Measured Results 67
Chapter 6 Conclusions and Future Work 70
6.1 Conclusions 70
6.2 Future work 70
References 71

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