臺灣博碩士論文加值系統

本論文的研究重點為U型槽金氧半電晶體(U shaped trench MOS)，此功率元件已被廣泛使用於汽車電子、驅動整流、電源供應等…各領域之上，其中本論文所探討之功率元件有最低導通電組(Lowest Ron)即為在使用下，所消耗的能量為最低，並能夠用於200V範圍內，且元件尺寸上為垂直Ｕ型槽，故能大幅減少面積，提高密集度。
本論文透過TCAD模套件，Tsuprem4建構元件製程與Sdevice、Medici軟體分析特性，其中UMOS之技術價值為FOM(figure of merit)=

With advances of semiconductor technology, integrated circuit, power device, switching device and motor driver are growth fast. The research focus on Power loss. The U-Sharped Trench MOSFET device is most of important. The reason is UMOS have Lowest On-Resistance and Operating range can be up to 200v. On-Resistance means when the power device turn-on it will cause power loss. And the UMOS are vertical U-Sharped trench design it is better than horizontal device. Due to vertical U-Sharped trench it can significantly reduce the chip size and increase the intensity.
Focus on this thesis used the Technology Computer Aided Design (TCAD) tool to develop the UMOS structure and reference by Technology company like Fairchild、Texas and TSMC specification to build the measurement circuit doing the Gate charge simulation、Switching loss measurement and Capacitance to analyze and improvement UMOS. Therefore, based on UMOS figure of merit = O

第一章 緒論 1
1.1 研究緣起 1
1.2 研究目的 3
1.3 模擬軟體 4
1.4 研究流程 5
1.5 論文架構 6
第二章 功率元件理論 7
2.1 介紹 7
2.2 功率元件的結構與操作 7
2.3 UMOS功率元件之優勢 8
2.4 雪崩崩潰(Avalanche Breakdown): 8
2.5 導通電阻(On-Resistance): 9
2.6 擊穿效應(Punch Through Breakdown): 10
2.7 臨界電壓（Threshold Voltage）: 10
2.8 RESURF (REduced SURface Field)原理: 10
2.9 氧化層崩潰(Oxide Breakdown): 12
2.10 U型溝槽設計(The U-Trench Design) 12
第三章 UMOS元件設計與模擬 13
3.1 UMOSFET製程流程: 13
3.2 使用TCAD模擬與設計元件: 20
第四章 功率損耗(Power Losses) 25
4.1 介紹: 25
4.2 元件示意圖 25
4.2.1 模擬之元件數量 26
4.3 閘極電荷理論與操作特性: 26
4.4 閘極電荷模擬量測 27
4.4.1 閘極電荷量測條件及波型圖 27
4.4.2 閘極電荷量測結果 28
4.5 切換損失理論與操作特性 30
4.6 切換損失模擬量測 31
4.6.1 切換損失量測條件及波型圖 31
4.6.2 切換損失量測結果 33
4.7 電容理論與操作特性 35
4.8 電容模擬量測 36
4.8.1 電容量測條件及波型圖 36
4.8.2 電容測試結果 36
4.9 能量損耗計算方程式 38
第五章 研究結果與建議 42
參考文獻 43
研究成果 46
致謝 47

圖目錄
　
圖 1.1 BCD Power IC Process Integration Technology 1
圖 1.2 超越摩爾定律以及後摩爾定律 2
圖 1.3 功率元件使用之頻率範圍 2
圖 1.4 功率元件使用之電壓與電流範圍 2
圖 1.5 閘極電荷(Gate Charge)輸入與波形圖 3
圖 1.6 切換損失(Switching loss)波形圖 3
圖 1.7 電容(Capacitance measurement)測試電容示意圖 4
圖 1.8 研究流程架構圖 5
圖 2.1 V-MOSFET結構之橫截面圖 7
圖 2.2 U-MOSFET結構之橫截面圖 8
圖 2.3 PN接面之雪崩崩潰電子電洞遷移現象 9
圖 2.4 理想的漂移區與電場分佈 9
圖 2.5 已發生擊穿現象之電晶體 10
圖 2.6 RESURF結構橫截面圖 11
圖 2.7 RESURF之表面電場 11
圖 2.8 陣列式U型溝槽設計[10] 12
圖 2.9 U型溝槽設計 12
圖 3.1 準備晶格為<100>且阻值為0.003歐姆的N型基板 13
圖 3.2 (a) Arsenic Drain RESURF磊晶層製程圖 13
圖 3.3 (b) Phosphorus Drain RESURF磷注入製程流程圖 13
圖 3.4 (a) Arsenic Drain RESURF進行退火製程，形成Arsenic RESURF層 14
圖 3.5 (b) Phosphorus Drain RESURF於P型參雜上，成長N型磊晶層，並且進行退火製程，形成Phosphorus RESURF層 14
圖 3.6　 使用全域佈值植入磷形成JFET層 14
圖 3.7　 採用多段式蝕刻及熱成長方式形成圓弧形Ｕ型溝槽 15
圖 3.8 　採用乾式氧化生長製程成長閘極氧化層 15
圖 3.9 　完成閘極需使多晶矽使其表面與矽基板齊平 16
圖 3.10　佈植P-Base層 16
圖 3.11　重摻雜佈植P+層 17
圖 3.12　重摻雜佈植N+層 17
圖 3.13　沉積BPSG層於元件表面形成平坦絕緣層 18
圖 3.14　定義出源極與金屬之接觸孔 18
圖 3.15　沉積鋁金屬進行金屬導線之佈局 19
圖 3.16　最終結構之UMOS元件設計示意圖 19
圖 3.17　模擬UMOS結構其根據佈局設計 20
圖 3.18　量測雪崩崩潰電壓電路示意圖 20
圖 3.19　砷和磷RESURF UMOS之雪崩崩潰電壓特性曲線 21
圖 3.20　量測臨界電壓電路示意圖 21
圖 3.21　砷和磷RESURF UMOS之臨界電壓特性曲線 22
圖 3.22　量測元件導通狀態之電路示意圖 22
圖 3.23　砷和磷RESURF UMOS之導通狀態下電壓電流特性曲線 23
圖 3.24　砷和磷RESURF UMOS未雪崩崩潰之表面電場分佈 23
圖 3.25　砷和磷RESURF UMOS雪崩崩潰後之表面電場分佈 24
圖 4.1　 模擬下的Drain RESURF UMOS結構圖 25
圖 4.2　 閘極電荷測試電路 26
圖 4.3 　UMOSFET汲極外加電壓輸入波型圖圖 26
圖 4.4 　通過UMOSFET汲極電流波型圖 27
圖 4.5　 閘極電荷波型圖 27
圖 4.6　 感測閘極電荷之汲極電壓電流、閘極輸入波型圖 28
圖 4.7　 時間與電荷關係圖，判斷元件內部電荷之現象 28
圖 4.8　 電荷與閘極電壓關係圖 29
圖 4.9　 切換損失測試電路 30
圖 4.10　汲極輸入開關切換波型圖 30
圖 4.11　閘極輸入開關切換波型圖 31
圖 4.12　汲極電流圖 31
圖 4.13　Fairchild Spec. FDB047N10閘極啟動、關閉時間 31
圖 4.14　閘極啟動、關閉時間之區段名詞 32
圖 4.15　閘極啟動、關閉時間之輸入圖 32
圖 4.16　Arsenic Drain RESURF切換損失圖 33
圖 4.17　Phosphorus Drain RESURF切換損失圖 33
圖 4.18　Arsenic和Phosphorus Drain RESURF汲極電流震盪 34
圖 4.19　Arsenic和Phosphorus Drain RESURF閘極震盪 34
圖 4.20　Arsenic和Phosphorus Drain RESURF閘極震盪 35
圖 4.21　電容測試電路 35
圖 4.22　電容量測 36
圖 4.23　Arsenic Drain RESURF電容量測 36
圖 4.24　Phosphorus Drain RESURF電容量測 37
圖 4.25　QGS2閘極-源極區電荷 38
圖 4.26　Fairchild Spec. FDB047N10 QGS2閘極-源極區電荷量 39
圖 4.27　Arsenic和Phosphorus Drain RESURF QGS2閘極-源極區電荷量 39

表目錄

表 3.1　 Arsenic and Phosphorus Drain RESURF特性表 24
表 4.1　 元件數量 26
表 4.2　 單一Cell電荷量測數 29
表 4.3　 達至100安培之電荷量測數 29
表 4.4 　電容量測研究 37
表 4.5　 功率損耗計算方程式 38
表 4.6　 單位名詞 38
表 4.7　 QGS2閘極-源極區電荷 39
表 4.8 　計算能量損耗 40
表 4.9　 導通狀態能量損耗計算 40
表 4.10　切換狀態能量損耗計算 41
表 4.11 閘極狀態能量損耗計算 41
表 4.12 能量損耗 41

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