臺灣博碩士論文加值系統

由於矽基電晶體具有低成本、高耐熱性和成熟的製造流程等優點，其在半導體工業上已發展超過了五十年。以矽元素當成通道材料的基礎上，我們研究了各種技術去改進元件效能在後摩爾時代，包含了單軸拉伸應力技術、鐵電閘極介電層技術和垂直堆疊式奈米片電晶體。
首先，我們研究一種能有效增強電晶體驅動電流的技術，應力。我們觀察到伸張型應力可簡單地由一層氮化矽覆蓋在閘極上產生，這能夠應用在無接面鰭式電晶體上，基板可為塊材矽或絕緣層上覆矽。在此研究中，相較於無伸張應力的電晶體，兩種基版含有伸張型應力的電晶體皆顯現出電流提升30%~40%的效果。此外，N型通道的無接面電晶體在此應力作用下，其臨界電壓偏移約0.1~0.3V。如果把無接面電晶體分別製做在塊材矽和絕緣層上覆矽的兩種基板上，在電晶體有同樣元件面積的情形下，以塊材矽為基板的電晶體顯可輸出較高的驅動電流，保有高度的競爭力。
接著，我們著手研究具有陡陗斜率的元件，有鐵電特性氧化層的電晶體。有鐵電特性氧化層的電晶體能使次臨界擺幅小於 60 mV/dec，可使電路在小供應電壓下操作。我們發現鐵電特性和元件通道大小有強烈的關聯。在小通道的具鐵電特性氧化層的電晶體上顯現出較多電荷缺陷特性，然而寬通道具有鐵電氧化層的電晶體顯現出較強的鐵電特性。為了獲得高效能具鐵電特性氧化層的電晶體，微影蝕刻製程應避免通道的側壁受到額外的蝕刻傷害。在元件經由5%氫氣的熱處理後，鐵電特性增強，且能夠同時減少半導體介面的缺陷密度。對P型和N型電晶體來說，經過氫氣的熱處理後，元件的次臨界擺幅小於60 mV/dec的比例上升。最後，我們展示了具有鐵電氧化層的電晶體製做的反相器。我們發現反相器的電壓傳輸特性曲線呈現了非單一方向的磁滯。當有鐵電氧化層的電晶體的反相器在電路中操作時，電壓傳輸特性曲線其磁滯方向隨著不同輸入電壓而變化，且要同時考慮供應電壓大小的因素。
最後，我們研究垂直堆疊無接面多晶矽奈米片電晶體。相較於閘極全包覆式和鰭式電晶體，在同樣的元件面積下，垂直堆疊奈米片結構擁有更高的效能，由於其有較大的等效通道面積。此外，相較於傳統的PN接面電晶體，無接面電晶體由於其製程簡單，且載子遷移率較不易受表面載子散射效應而下降，更加地引人注目。製做無接面多晶矽奈米片電晶體包含兩個主要步驟，乾蝕刻和濕蝕刻。通道厚度由乾蝕刻決定，而通道寬度縮減則由濕蝕刻所控制。相較於單通道的電晶體，堆疊式的N型和P型電晶體擁有更高的導通電流，這是由於垂直堆疊式電晶體擁有較大的等效通道面積。最後，藉由分別調整N型和P型電晶體的通道寬度可獲得較對稱的輸出電流，使得具有垂直堆疊奈米片結構的反相器其電壓傳輸特性曲線能夠較對稱，不僅能縮小雜訊容限且不會增加更多元件面積。
除了傳統的反相器，我們也利用垂直堆疊奈米片的結構製做互補式電晶體反相器。相較於傳統的反相器，互補式電晶體反相器能減少50%元件面積和擁有較少的製程步驟。然而，互補式電晶體反相器，無法分別透過調整N型和P型電晶體通道大小，去調整電壓傳輸特性曲線。這是因為在互補式電晶體結構中，P型半導體位於N型半導體之上，P型和N型電晶體輸出電流的比例不大會隨著通道大小而變化。我們利用校正過的SPICE模組來模擬互補式電晶體反相器。相較於傳統的反相器，互補式電晶體反相器有較低的輸入電容，因此在電路上顯現出較少的延持時間且同時具備低功耗特性。我們利用垂直堆疊奈米片結構製做出了傳統反相器和互補式電晶體反相器，所有製程溫度皆小於600度，在3D ICs的製程上開創了新的契機。

Si-based transistors have been widely used in the last 50 years in the semiconductor industry because of their low cost, high thermal stability, and mature fabrication process. We investigate various techniques to improve the performance of Si-based transistors in the post-Moore era, including the uniaxial strained technique, ferroelectric gate dielectric, and vertically stacked nanosheet (NS) transistors.
First, we investigate the strained technology to effectively enhance the current drivability of metal-oxide-semiconductor field-effect transistors (MOSFETs). It is observed that uniaxial tensile strain is generated easily by capping a SiNx layer on a gate electrode, which could be applied to a bulk junctionless (JL) fin field-effect transistor (FinFET) or JL silicon-on-insulator field-effect transistor (SOIFET). In this study, both of these types of strained JL-FETs show Ion enhancement of up to around 30%–40% compared to unstrained ones. Moreover, strained technology shifts the VTH of n-channel JL-FETs by 0.1–0.3 V. JL bulk FinFETs with the same footprint and high Ion can show performance comparable to that of JL SOIFETs.
Next, we study ferroelectric FETs (FeFETs), a type of steep-slope device. FeFETs allow subthreshold swing (SS) below 60 mV/dec, enabling integrated circuits to be operated with small VD. The ferroelectric properties are found to strongly depend on the channel width. FeFETs with a narrow channel show more charge-trapping-dominated properties, whereas those with a broad channel show stronger ferroelectric properties. To fabricate high-performance FeFETs, lithography and dry etching processes must be performed carefully so as to reduce additional sidewall roughness and damages. By applying forming gas annealing (FGA), the ferroelectricity of HZO is improved and the trap density at the interface is simultaneously decreased. For n-type FETs (NFETs) and p-type FETs (PFETs), the percentage of working devices with SS below 60 mV/dec increases after performing FGA. Finally, we demonstrate a FeFET complementary metal-oxide-semiconductor (CMOS) inverter. It is observed that the voltage transfer characteristic (VTC) hysteresis does not show only one direction. As a FeFET inverter is operated in an integrated circuit, the variation in VTC hysteresis with different Vin and VD should also be considered.
Finally, vertically stacked JL poly-Si NSFETs are investigated. A vertically stacked NS structure can enhance the device performance by increasing the effective device width compared with gate-all-around (GAA) nanowire transistors and FinFETs in a given footprint. Moreover, compared to inversion-mode FETs, JL-FETs are attractive owing to the possess simplicity and immunity of mobility degradation of carriers scattering at the channel/oxide interface. The fabrication of JL poly-Si NSs involves two main etching processes: dry etching and wet etching. The channel thickness is controlled by dry etching, and the channel width is shrunk down by wet etching. Compared to a device with a single channel, stacked N/PFETs show higher on-current. This is owing to the larger effective width of the vertically stacked NS. By adjusting the NS channel width for N/PFETs, the VTCs of the CMOS inverter can be matched much better via on-current matching without area penalty.
In addition to conventional CMOS inverters, a complementary field-effect transistor (CFET) inverter is also fabricated on a vertically stacked poly-Si NS structure. Compared with a conventional CMOS inverter, a CFET inverter has 50% smaller footprint and requires fewer fabrication steps. However, the VTCs of a CFET inverter cannot be adjusted by varying the WN/WP ratios. Because the PFET is over the NFET in a CFET structure, ID of N/P-channel NSFETs vary together. Calibrated SPICE simulations show that a CFET has lower input capacitance, and therefore, a smaller delay and reduced power consumption, when compared with a standard CMOS. The new configuration of CFET inverters and CMOS inverters at low temperature (≤600°C) on stacked NSs demonstrated experimentally in this study should provide new opportunities for monolithic 3D integration.

Abstract (Chinese) i
Abstract (English) iii
Acknowledgement (Chinese) vi
Contents vii
List of Tables x
List of Figures xi
Chapter 1 Introduction 1
1.1 General Background 1
1.2 Strained Technology 3
1.3 Ferroelectric FETs 4
1.4 Vertical Stacked Gate-all-around Transistor 5
1.5 Motivation 7
1.6 Organization of the Research 8
Chapter 2 Uniaxial Tensile Strained n-channel JL SOI FETs and Triangular JL Bulk FinFETs for nano-scaled Applications 14
2.1 Introduction 14
2.2 Experimental Procedure 16
2.2.1 Fabrication of the JL SOI FET 16
2.2.2 Fabrication of the JL bulk FinFET 16
2.3 Results and Discussions 17
2.3.1 Electrical Characteristic of the JL SOI FETs 17
2.3.2 Electrical Characteristic of the JL bulk FinFET 18
2.3.3 Analysis of leakage current in JL bulk FinFETs 19
2.3.4 Comparison of the JL bulk FinFET and JL SOI FET 20
2.4 Summary 21
Chapter 3 Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter 30
3.1 Introduction 30
3.2 Experimental Procedure 31
3.2.1 Fabrication of the FeFET 31
3.3 Results and Discussions 32
3.3.1 Effect of FGA on FeFETs 32
3.3.2 Effect of channel dimensions on FeFETs 34
3.3.3 Characterization of a FeFET Inverter 36
3.4 Summary 37
Chapter 4 Fabrication of Vertically Stacked Nanosheet Junctionless Filed-Effect Transistors and Applications for the CMOS Inverters 46
4.1 Introduction 46
4.2 Experimental Procedures 47
4.2.1 Fabrication of the vertically stacked NS 47
4.3 Results and Discussions 49
4.3.1 Dopant Diffusion and Surface Roughness 49
4.3.2 Electrical Characteristics of Stacked NS N/PFETs 49
4.4 Summary ..51
Chapter 5 CMOS Inverter Based on GAA CFETs Structure for 3D-IC Applications 62
5.1 Introduction 62
5.2 Device Fabrication 63
5.2 Results and Discussions 64
5.2.1 Electrical Characteristics of N/PFETs 64
5.2.2 Electrical Characteristics of CFET 64
5.2.3 CFET Simulation 65
5.3 Summary 66
Chapter 6 Conclusions and Recommendations for Future Research 75
6.1 Conclusions 75
6.2 Recommendations for Future Research 76
6.2.1 CFET inverter with multiple channels 76
6.2.2 Vertical Nanowire Transistor 77
Reference 78
Publication List 99
Vita 103

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